Analysis Of Electrical Characteristics Research Articles

Mechanical and electrical characteristics analysis of the ACSR affected by high temperature

Generally, the characteristics of the conductor that was affected by forest fire can be analyzed only when the forest fire is accurately modeled and its effect is identified. Few studies have been conducted with a forest fire model for transmission lines, and no results of the examination of the actual test specimens that were exposed to forest fire have been reported. As the dust characteristics of a forest fire are difficult to analyze in the actual field, an environment that was similar to that in the field was used in this study. Dust was deposited on a wire using an artificial dust experiment device by distance, to test and analyze the temperature and mechanical and electrical characteristics. It seems that this analysis data in this study can be used as the basic data for the database that can be utilized to analyze wires exposed to forest fire flames and dust and to predict the ACSR wire refurnish life.

Analysis of Electrical Characteristics of Photovoltaic Single Crystal Silicon Solar Cells at Outdoor Measurements

The electrical performance of a photovoltaic (PV) silicon solar cell is described by its current–voltage (I–V) character-istic curve, which is in turn determined by device and material properties. In this study, an investigation of the performance and device parameters of photovoltaic single crystalline silicon (Si.) solar cell of the construction n+pp++ PESC(Passivatted Emitter Solar Cell) at different conditions of solar irradiance, title angle and mirror boosting effects had been studied. Also the paper reports on the performance data of the Si. cell, using standard I–V characteristic curves to obtain output parameters and to show that there are possible performance degrading defects presents.

Reliability issues of Gallium Nitride High Electron Mobility Transistors

In the present paper we review the most recent degradation modes and mechanisms recently observed in AlGaN/GaN (Aluminum Gallium Nitride/Gallium Nitride). High Electron-Mobility Transistors (HEMTs), as resulting from a detailed accelerated testing campaign, based on reverse bias tests and DC accelerated life tests at various temperatures. Despite the large efforts spent in the last few years, and the progress in mean time to failure values, reliability of GaN HEMTs, and millimeter microwave integrated circuits still represent a relevant issue for the market penetration of these devices. The role of temperature in promoting GaN HEMT failure is controversial, and the accelerating degradation factors are largely unknown. The present paper proposes a methodology for the analysis of failure modes and mechanisms of GaN HEMTs, based on (i) DC and RF stress tests accompanied by an (ii) extensive characterization of traps using deep level transient spectroscopy and pulsed measurements, (iii) detailed analysis of electrical characteristics, and (iv) comparison with two-dimensional device simulations. Results of failure analysis using various microscopy and spectroscopy techniques are presented and failure mechanisms observed at the high electric field values typical of the operation of these devices are reviewed.

A new method for stable numerical differentiation

In this paper, we proposed a new algorithm for stable numerical differentiation by optimizing node intervals. With the algorithm, noise-free differentiated values can be extracted within one-percent error. By overcoming noise problem due to numerical differentiation process, our algorithm can easily extract the differentiated values. Also, it can be extended to high order differentiation. To confirm the proposed algorithm, we applied it to the analysis of MOSFET electrical characteristics. It will provide us with a useful analysis tool in the field of parameter extraction from numerical data such as device characterization.

Optimization of the Fabrication Process for ZnO Thin-Film Transistors with HfO2 Gate Dielectrics

In this work, we address the analysis of ZnO thin films and electrical characteristics of ZnO thin film transistors (TFTs) with HfO2 high-k gate dielectrics after low-temperature postannealing. The SIMS analysis shows that the diffusion of Zn atoms into the HfO2 gate dielectrics will occur after 300 °C annealing and the related electrical characteristics indicate that 200 °C annealing will be the suitable annealing condition for ZnO/HfO2/ITO-based TFTs. The ZnO TFTs after 200 °C annealing exhibited transistor behavior over the range of 0–7 V; the field effect mobility, subthreshold slope, and on/off ratio were measured to be 1.3 cm2 V-1 s-1, 0.5 V/decade, and ∼106, respectively.

Predicting the technical impacts of high levels of small-scale embedded generators on low-voltage networks

The anticipated high penetrations of small-scale embedded generators (SSEGs) on public low-voltage (LV) distribution networks are likely to present distribution network operators (DNOs) with a number of technical impacts relating to power quality, distribution system efficiency and potential equipment overloads. Impact studies need to be performed using suitable case study networks in order to evaluate the effects of SSEGs on LV distribution networks and quantify allowable SSEG penetration levels. The aim is to propose a methodology for predicting the technical impacts of SSEGs on LV networks without the need for developing a detailed computer-based model of the power system and simulating a range of operating scenarios. This methodology is drawn from an analysis of the key electrical characteristics that determine the response of LV networks to the addition of SSEGs, focusing on the following technical aspects: (i) voltage regulation, (ii) voltage rise, (iii) voltage unbalance, (iv) cable and transformer thermal limits and (v) network losses. The analysis is carried out on a UK generic and a European generic LV network and simulation results for both networks are presented and discussed. The proposed methodology is then applied to an existing public UK LV network operated by E.ON UK Central Networks, indicating a good agreement between predicted and simulation results.

Low Temperature Post-Annealing of ZnO Thin-Film Transistors with High-k Gate Dielectrics

This work addresses the thin film analysis of ZnO and electrical characteristics of ZnO TFTs with HfO2 high-k gate dielectrics after low temperature post-annealing. The SIMS analysis shows that the diffusion of Zn atoms into the HfO2 will occur after 300 oC annealing and the related electrical characteristics indicates that the 200 oC annealing will be the optimized annealing condition for the ZnO/HfO2/ITO based TFTs. The ZnO TFTs after optimized annealing condition exhibited transistor behavior over the range 0-7 V; the field effect mobility, subthreshold slope and on/off ratio were measured to be 1.3 cm2V-1s-1, 0.5 V/decade and ~106, respectively.

Analysis of temperature dependent electrical characteristics of Au/n-GaAs/GaAs structures in a wide temperature range

The temperature dependence of some electrical parameters of Au/n-GaAs/GaAs structures obtained from the forward bias current–voltage ( I– V) and reverse bias capacitance–voltage ( C– V) characteristics is studied in the temperature range of 79–400 K. The forward bias current I is found to be proportional to I o( T)exp( AV), where A is the slope of Ln( I) –V curves and almost independent of the voltage and temperature, and I o( T) is relatively a weak function of temperature. The semi-logarithmic Ln( I)– V characteristics based on the thermionic emission (TE) mechanism showed a decrease in the ideality factor ( n) and an increase in the zero-bias barrier height ( Φ Bo) with increasing temperature. These behaviors don't obey the pure thermionic emission (TE) theory. However, the barrier height Φ B( C– V) determined from the C −2– V plot at high frequency decreased linearly with the temperature. Analysis of the data indicated that the predominant current conduction mechanism of our sample was a trap-assisted multistep tunneling rather than the other mechanisms.

Analysis of electrical characteristics of Au/SiO 2/n-Si (MOS) capacitors using the high–low frequency capacitance and conductance methods

The purpose of this paper is to analyze electrical characteristics in Au/SiO 2/n-Si (MOS) capacitors by using the high–low frequency ( C HF– C LF) capacitance and conductance methods. The capacitance–voltage ( C– V) and conductance–voltage ( G/ω– V) measurements have been carried out in the frequency range of 1 kHz–10 MHz and bias voltage range of (−12 V) to (12 V) at room temperature. It was found that both C and G/ω of the MOS capacitor were quite sensitive to frequency at relatively low frequencies, and decrease with increasing frequency. The increase in capacitance especially at low frequencies is resulting from the presence of interface states at Si/SiO 2 interface. Therefore, the interfacial states can more easily follow an ac signal at low frequencies, consequently, which contributes to the improvement of electrical properties of MOS capacitor. The interface states density ( N ss) have been determined by taking into account the surface potential as a function of applied bias. The energy density distribution profile of N ss was obtained from C HF– C LF capacitance method and gives a peak at about the mid-gap of Si. In addition, the high frequency (1 MHz) capacitance and conductance values measured under both reverse and forward bias have been corrected for the effect of series resistance ( R s) to obtain the real capacitance of MOS capacitors. The frequency dependent C– V and G/ω– V characteristics confirm that the N ss and R s of the MOS capacitors are important parameters that strongly influence the electrical properties of MOS capacitors.

Low-temperature polysilicon thin film transistors on polyimide substrates for electronics on plastic

In this work we show a new low-temperature polycrystalline silicon (LTPS) thin film transistor (TFT) fabrication process on polyimide (PI) layers. The PI is spun on Si-wafer used as rigid carrier, thus overcoming difficulties in handling flexible freestanding plastic substrates, eliminating the problem of plastic shrinkage with high temperature processing and allowing the use of standard semiconductor equipment. LTPS TFTs are fabricated according to a conventional non self-aligned process, with source/drain contacts formed by deposition of a highly doped Si-layer and patterned by a selective wet-etching. Laser annealing is performed providing simultaneous dopant activation and crystallization of the active layer. The maximum process temperature is kept below 350 °C. After LTPS TFTs fabrication, the PI layer is mechanically released from the rigid carrier, which can be re-used for a new fabrication process. The devices exhibit good electrical characteristics with field effect mobility up to 50 cm 2/V s. Analysis of electrical stability and characteristics in presence of mechanical stress is also shown.

Further investigation of a hydrogen-sensing Pd/GaAs heterostructure field-effect transistor (HFET)

Abstract Based on a GaAs-based heterostructure field-effect transistor (HFET) equipped with a catalytic Pd gate, an interesting Pd/GaAs transistor-type hydrogen sensor is fabricated and studied. A simple model is used to elucidate the on-state and off-state behaviors in the transistor operation. In air and N 2 environments, hydrogen-induced effect not only causes an obvious current variation in the saturation region, but also results in a drastic change of sensor response in the cut-off region. The further analyses of electrical characteristics are also presented. The calculated values of I DS operating regime (>0.8 g m,max ) are 115.3 (115.1) and 108.2 (106.2) mA/mm in air (N 2 ) and 1% H 2 /air (1% H 2 /N 2 ), respectively. The variation trend of g m under the positive gate bias is contrary to that under the negative gate bias in hydrogen-containing ambiance. In addition, the decrease in on–off current ratio ( I on / I off ) towards hydrogen gas is attributed to the considerable variation of I off in the cut-off region.

Numerical Analyses of Electrical Contact Characteristics of YBCO Bulk With Silver Deposition

In this paper, an axial symmetric model is constructed to investigate the electrical contact characteristics of YBCO bulk with silver deposited on the contact surface. In order to calculate the thermal-electromagnetic coupling characteristics near the contact spot, a series expression is derived to describe the quenching behavior of YBCO bulk based on the power law and Kim model and a detailed thermal-electromagnetic coupling process is presented according to the physical quenching process of YBCO bulk. During the calculation, the thermal field, the electrical field, and the self-magnetic field are coupled with each other. The calculated contact resistances are compared with the experimental ones. Agreements between them verify the effectiveness of the axial symmetric model. At last, a detailed description about the contact resistance changing from the low-impedance state to the high-impedance state is given based on the calculated field distributions. This work could be helpful to further understanding the electrical contact characteristics of YBCO bulk.

NOISE CHARACTERISTICS AND RELIABILITY OF LIGHT EMITTING DIODES BASED ON NITRIDES

Optical and electrical noises and correlation factor between optical and electrical fluctuations of nitride-based light emitting diodes (LEDs) have been investigated under forward bias. Their electrical, optical and noise characteristics were compared with ones of LEDs of other materials. LED noise characteristic changes during aging have been measured, too. It is found that optical and electrical noise spectra under forward bias for more reliable LEDs distinguish by lower l/f type fluctuations and Lorentzian type noise at higher frequencies. LEDs with intensive 1/f noise demonstrate shorter lifetime. It is shown that reason of LED degradation is related with defects presence in device structure. These defects can be formed during device fabrication or appear during operation. An analysis of LED current-voltage and electrical noise characteristics under forward and reverse bias has shown that LEDs with intensive 1/f electrical noise, large reverse current (low reverse breakdown voltage) and larger terminal voltage under forward bias distinguish by short lifetime.

Analysis of rotary electrical discharge machining characteristics in reversal magnetic field for copper-en8 steel system

The material removal rate (MRR), along with the electrode wear rate (EWR), plays an important role in analysing machine output during electrical discharge machining. This work focuses on the improvement of machine output by introducing an induced magnetic field on the workpiece during rotary electrical discharge machining (REDM) of EN-8 steel with a rotary copper electrode. The workpiece was placed inside the induced magnetic field, wherein polarity of the magnetic field gets reversed periodically. Using Taguchi’s recommended design of experiments, we initially conducted experiments with eight input parameters at different levels . Significant parameters were identified with the help of the signal-to-noise ratio and ANOVA. Finally, another set of experiments was conducted for analysis of the process and development of empirical expressions for MRR and EWR. Experimental results established that rotary electrical discharge machining with a polarity reversal magnetic field delivers better machining output than machining in a non-magnetic field. Thus, this work benefits the EDM process by reducing the machining costs and by producing better geometrical trueness on workpieces, as MRR increased and EWR decreased.

복합 가속열화를 통한 배전용 고분자 피뢰기의 장기 열화특성 예측

In this study accelerated aging test equipment was developed to simulate domestic weather condition for accelerated aging test of polymer housed distribution surge arresters. Polymer arresters were aged for 3,000 hours by this test equipment and chemical and electrical characteristics analysis of surge arresters were conducted after aging test. In addition, performance assessment of outdoor installed arresters for 3 years was conducted to compare aging effect between accelerated aging test and natural aging. Through this experiment it is verified that the capability of the proposed aging test for simulating natural aging and the housing material and disconnector of domestic polymer arresters can be deteriorated by the long time field operation.

Experimental Analysis of Mechanical and Electrical Characteristics of Metal-Coated Conductive Spheres for Anisotropic Conductive Adhesives (ACAs) Interconnection

An accurate characterization for the deformation behavior of conductive particles is important: 1) to understand the anisotropic conductive adhesive (ACA) interconnection and 2) to optimize the ACA bonding parameter. This paper introduces an experimental technique, which has been developed to allow continuous monitoring of deformation characteristics of a single conductive particle. The load-deformation curve of a single conductive particle is measured, which provides the quantitative estimation of the mechanical and electrical characteristics of metal-coated polymer spheres used in ACAs. Based on the load-deformation result of a single conductive particle and the number of trapped particles on a bump, equivalent spring models are used to predict the deformation degree of conductive particles after flip chip assembly. For two kinds of conductive particles with different polymer cores, the mechanical and electrical characteristics of ACA interconnection were studied. Such results are used to further achieve a more sophisticated approach of the ACA bonding process and contact reliability

Analysis of electrical characteristics of high performance pentacene thin-film transistors with PMMA buffer layer

Top contact and bottom contact TFTs, based on evaporated pentacene, have been fabricated by using PMMA as buffer layer. Both type of devices show high performance with field-effect mobility >1cm2/Vs. Top contact transfer characteristics, measured at different temperatures, have been analyzed by the ‘temperature method’ in order to evaluate the effective density of localized states (DOS). The calculated DOS, approximated by two exponential tails, has been used in 2D numerical device analysis program to simulate the transfer and output characteristics at different temperatures.

Small‐signal characteristics of organic semiconductors with continuous energy distribution of traps

AbstractThe electrical characteristics of organic light emitting devices containing a continuous distribution of trap states in the forbidden gap are obtained by numerically solving the basic semiconductor equations for the steady state and under small‐signal conditions. The spatially‐dependent occupied trap states, which are described by an explicit density of states function, modify the charge distribution within the structure and the shape of the electric field and the carrier current densities. The effect of the modulation frequency, the applied voltage and the device temperature are studied for a hole conducting layer with a trap density of states consisting of a double gaussian profile and for a given set of microscopic parameters including the carrier mobilities and thermal velocities, the capture cross sections, and the residual shallow impurity concentration. The frequency‐dependent loss and capacitance curves are obtained for various experimental conditions, like temperature and applied steady‐state voltage. Effects of parameters describing electrical contacts and trap density of states are shown. Such results are particularly useful for the analysis of experimental electrical characteristics obtained by thermal admittance spectroscopy. (© 2005 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Evaluation of trap states at front and back oxide interfaces and grain boundaries using electrical characteristic analysis and device simulation of polycrystalline silicon thin‐film transistors

AbstractThe trap states at the front and back oxide interfaces and grain boundaries of polycrystalline silicon thin‐film transistors are evaluated by using electrical characteristic analysis and device simulation. First, the method for extracting the trap densities of the front and back oxide interfaces and the grain boundaries is explained as the electrical characteristic analysis. When applied to the diagnosis of actual transistor characteristics, we see that oxygen plasma treatment or vapor heat treatment effectively decreases the trap densities at the front and back oxide interfaces, and self‐heating degradation increases the trap densities at the front and back oxide interfaces. Next, we use device simulation to examine the dependence of the transistor characteristics on the trap densities. When the simulation results were similarly applied to the diagnosis of actual transistor characteristics, we see that the oxygen plasma treatment naturally reduced the trap densities at the oxide interfaces, and the plasma‐enhanced chemical‐vapor deposition of tetraethylorthosilicate increased the trap densities at the grain boundaries. In a systematic summary of these analysis results, the effects of the trap states on the transistor characteristics, the improvement method, and the causes of degradation are discussed. © 2005 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 88(2): 1–10, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20124

Cadmium sulfide thin-film transistors fabricated by low-temperature chemical-bath deposition

In this paper, we report the characterization and analysis of the dc electrical characteristics of thin-film transistors fabricated from low-temperature chemical-bath-deposited CdS as the channel layer. Our analysis shows that the device can be operated either in the depletion mode or in the accumulation mode. In the depletion mode, the channel lies completely within the bulk of the CdS layer. In the accumulation mode, the current is carried by an accumulation channel at the SiO2∕CdS interface and a buried channel that lies in the bulk of the CdS layer. Using our device analysis, we have extracted the threshold voltage, the carrier concentration in CdS, and the carrier mobility in the bulk channel as well as in the surface channel. The extracted value of the surface channel mobility is found to be greater than 1cm2∕Vs, which shows that the CdS deposited by this method has a great promise for applications that require low-temperature processing (e.g., in plastic electronics).