Advanced Packaging Research Articles

Influence of Rigid Carrier Substrates & its Release Layer on Ultra Fine Pitch chip last FO-WLPs

In recent years the leading-edge product enablers in Wireless Connectivity for WiFi & Bluetooth, Wearable HD Modules, Artificial Intelligence (AI), Application Processors etc. require ultra-high density chip packaging device using heterogenous integration to constructing the SiP modules. In order to meet their requirements, fan-out chip last WLP – having its redistribution layer (RDL) constructed first – is definitely the solution of choice to assemble devices in such advanced packaging platforms. This approach further eliminates known good die (KGD) loss risk, resulting in higher assembly yield and lower cost. Rigid carrier substrate and the release layer placed on top of it influences the process yield of fan-out chip last WLP. It gets more challenging when ultra-fine pitch redistribution layers (RDL) are required. This paper focuses on the influence of release layer on quality of narrow line & space RDL, as well as on the separation force during debonding. It further describes an optimized solution through HRDP® (High Resolution Debondable Panel) technology, which is the most compatible carrier to fabricate the leading-edge fan-out chip last process. The HRDP® carrier is offered in various dimensions and thicknesses as round wafers and square/rectangular panels with glass or silicon to match customer requirements. This is made of 100% inorganic material, which helps to improve interfacial stresses and facilitates debonding. During processing, this inorganic release layer (IRL) demonstrates higher chemical resistance and heat resistance than alternative technology such as the laser lift-off (LLO) type carrier.

Addressing Challenges in Dual Sided SiP Thermal Budget

System-in-Package (SiP) has been adopted as the mainstream advanced packaging technology in many consumer applications including 5G smartphones, tablets, wireless earbuds, smart wearables, etc. Heterogeneous integration, smaller form factor, better electrical performance, lower cost of assembly and faster time to market are the key differentiators of SiP as compared to conventional packaging techniques. In applications such as 5G mobile RF Front-End (RFFE) and Antenna-in-package (AiP) modules, dual sided SiP is the popular approach which brings even higher level of integration and smaller form factor. However thermal warpage control is a significant challenge during two times of solder reflow processes for the front and back sides of the package, especially if one side is with underfill and mold materials which have significant CTE mismatch to the substrate and dies, causing delamination failures and yield losses. This study examines the novel solution of reducing thermal budget with the use of a low temperature solder paste material based on SnBiAg alloy in ultra-fine pitch Type 6 solder powders. It allows a minimal peak reflow temperature of only 170 °C that effectively reduces warpage of dual sided SiP substrates. Solder alloy and paste properties and solder joint microstructures are examined in detail for tests including fine-pitch printing and component soldering, thermal aging test on different substrate finishes, thermal cycling test and mechanical drop test for reliability performance.

Back End Commonality for Advanced Packaging: Large Form Factor Project

Address key gaps for advanced packages through complex assembly processes and provides flexibility for handling different body size package • Enable new products and product segments not limited by current JEDEC body sized •Demonstrates the cost effectiveness of leveraging tool commonality • Increase Backend operational efficiency • Define large form factor product handling media that allows for flexibility and higher density • Ability to maximize footprint: # of packages in held in the “handling media” • Minimize tooling changeover times • Provide the same “outer design” for many different package sizes/types, thereby minimizing NRE and Increased Tool Flexibility

Hybrid Bonding for the Next Generation of High -Performance Devices

The electronics industry continues to pursue optimal performance for the insatiable consumer demand of computation intensive products like GPUs, CPUs and AI accelerators. While the monolithic system on chip approach promises exceptional performance, it is costly. The advanced packaging industry has responded to the challenge with 2.5D and 3D integration solutions that bridge the performance gap with heterogeneous integration. Hybrid bonding combined with chiplet architectures within 2.5D will enable the distribution of function and nodes across a chips within a module, providing a path toward more flexible product introduction and innovation. The design and manufacturing of chip-to chip-communication is complex and has some technology dependencies. One technology limitation in realizing a monolithic performance with heterogeneous integration is solder interconnect scalability. Hybrid bonding is a revolutionary platform technology that solves the interconnect scalability problem and delivers enhance performance compared to the conventional Cu microbump. The Direct Bond Interconnect (DBI®), more generally known as hybrid bonding, offers a performance boost that enables novel 3D architectures via disaggregation and chiplet implementation, in spite Moore’s law slowing. The efficient interconnect between circuit functions at the wafer, die and package level, will fuel semiconductor company roadmaps for decades. The performance advantages, ease of integration of such a hybrid interconnect will be discussed in chip to wafer and chip to chip applications. The key areas of innovation anticipated to proliferate the technology within the entire advanced packaging supply chain will be presented.

Heterogeneous Integration with 3D Packaging

The next generation of competitive integrated devices demand increased device density, higher memory bandwidth, reduced global interconnects, increased energy efficiency (with higher performance), and a smaller footprint. With the slowdown in Moore’s law and the advancements in chiplet architectures, which are now recognized as fundamental to enabling the continued economically viable growth of power efficient computing, advanced packaging technologies and architectures are becoming more critical to enabling Moore’s Law’s next frontier through heterogeneous integration. In this presentation, we will cover the advanced package architectures being enabled by AMD to enable power, performance, area, and cost (PPAC) improvements as well as enable heterogeneous architectures. The direct Cu-Cu bonding technology used in AMD 3D V-Cache architecture will be detailed and compared to industry standard 3D architectures.

Advanced Packaging: Enabling Moore’s Law’s Next Frontier Through Heterogeneous Integration

With chiplet architectures becoming mainstream, and recognized as fundamental to enabling the continued economically viable growth of power efficient computing, advanced packaging technologies and architectures are becoming more critical to enabling Moore’s Law’s next frontier through heterogeneous integration. In this tutorial, we will cover the advanced package architectures being enabled by AMD to enable PPAC (power, performance, area and cost) improvements as well as enable heterogeneous architectures. The direct Cu- Cu bonding technology used in AMD’s 3D VCache architecture will be detailed and compared to industry standard 3D architectures for PPAC benefits. Other technologies that are being enabled to advance high performance computing architectures will also be previewed.

Novel cellulose nanocrystal/metal-organic framework composites: Transforming ASA-sized cellulose paper for innovative food packaging solutions

In this study, a novel cellulose nanocrystal/metal-organic framework composite (MC) was developed as a stabilizer for alkenyl succinic anhydride (ASA) Pickering emulsions, demonstrating remarkable sizing performance and antimicrobial properties for advanced food packaging applications. The MCs exhibited superior emulsion stabilization capabilities compared to pure metal-organic frameworks, with the optimum MC concentration identified as 1.0 wt% CNC. The hydrophobicity of the sizing paper was found to be enhanced with increasing CNC content. The MC-ASA sized paper demonstrated commendable storage stability, robust gas adsorption, and resistance to water vapor or water droplets. The MCs-ASA sized paper showed excellent food preservation efficacy, maintaining the freshness of strawberries for up to seven days, compared to ASA-sized paper without MCs. The antimicrobial assays targeting Escherichia coli and Staphylococcus aureus highlighted the intrinsic antimicrobial properties of the MCs, contributing to the extended freshness of the encased strawberries. The water vapor barrier efficacy and water retention capabilities of MCs-ASA sized paper were found to be superior to those of the paper without MCs, emphasizing the potential of the developed composite as an innovative and effective food packaging solution. This study offers valuable insights into the synthesis and implementation of CNC/MOF composite particles for versatile applications in food packaging, water-resistant materials, and environmental protection.

Addressing Power and Thermal Challenges in Advanced Packaging for AI CPUs/GPUs: Insights into Multi-die Stacking Technology

The rapid advancement of artificial intelligence (AI) has propelled the demand for high-performance computing systems, leading to significant challenges in power and thermal management in advanced packaging for AI CPUs/GPUs. This research paper explores various strategies and technologies to address these challenges. It examines the principles and types of multi-die stacking technology, power optimization techniques, and advanced thermal management solutions. Furthermore, the paper discusses the integration of power and thermal management strategies and their synergistic effects. Case studies and numerical analyses highlight the effectiveness of these approaches in improving energy efficiency, performance, and reliability in AI semiconductor devices. The paper also identifies emerging technologies, such as heterogeneous integration and chiplet-based architectures, and outlines future directions for innovation in advanced packaging. Overall, by leveraging comprehensive research and collaboration, the semiconductor industry can drive the development of advanced packaging solutions that meet the growing demands of AI workloads and enable transformative advancements across industries and applications.

Nanotwinning-assisted structurally stable copper for fine-pitch redistribution layer in 2.5D/3D IC packaging

The redistribution layer (RDL) is crucial for fanning out circuits and for 2.5D/3D IC packaging. As device density increases, RDL CD/pitch must shrink. During RDL circuit fabrication, the etching process is necessary to remove the exposed sputtered Cu seed layer and Ti barrier layer. Unfortunately, this process unavoidably etches and roughens the Cu surface of the RDL. As the post-plating resting time (q-time) increases, the Cu surface oxidizes, resulting in even worse surface roughness after etching. This roughness causes contact resistance and electromigration issues when the RDL linewidth shrinks. This paper presents a composite Cu structure that combines fine grains and nanotwins, which is structurally stable and can effectively resist surface damage even after extended periods, offering a promising solution for achieving finer RDL in advanced packaging technologies with a longer electromigration lifetime than regular coarse-grain lines.

Power Electronics Revolutionized: A Comprehensive Analysis of Emerging Wide and Ultrawide Bandgap Devices.

This article provides a comprehensive review of wide and ultrawide bandgap power electronic semiconductor devices, comparing silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and the emerging device diamond technology. Key parameters examined include bandgap, critical electric field, electron mobility, voltage/current ratings, switching frequency, and device packaging. The historical evolution of each material is traced from early research devices to current commercial offerings. Significant focus is given to SiC and GaN as they are now actively competing with Si devices in the market, enabled by their higher bandgaps. The paper details advancements in material growth, device architectures, reliability, and manufacturing that have allowed SiC and GaN adoption in electric vehicles, renewable energy, aerospace, and other applications requiring high power density, efficiency, and frequency operation. Performance enhancements over Si are quantified. However, the challenges associated with the advancements of these devices are also elaborately described: material availability, thermal management, gate drive design, electrical insulation, and electromagnetic interference. Alongside the cost reduction through improved manufacturing, material availability, thermal management, gate drive design, electrical insulation, and electromagnetic interference are critical hurdles of this technology. The review analyzes these issues and emerging solutions using advanced packaging, circuit integration, novel cooling techniques, and modeling. Overall, the manuscript provides a timely, rigorous examination of the state of the art in wide bandgap power semiconductors. It balances theoretical potential and practical limitations while assessing commercial readiness and mapping trajectories for further innovation. This article will benefit researchers and professionals advancing power electronic systems.

Food Packaging Innovation to Extend Shelf Life and Reduce Food Waste in a Leading Company in Indonesia

This research investigates the impact of food packaging innovations on shelf life extension and food waste reduction within a leading Indonesian food company. Employing a quantitative approach, the study incorporates a diverse sample of products subjected to various packaging technologies. Descriptive and inferential statistics reveal a statistically significant increase in shelf life by 50% and a substantial reduction in food waste by 40%. Consumer surveys underscore positive perceptions, with 80% expressing a preference for sustainable packaging. Economically, a 15% reduction in costs associated with product losses supports the business case for innovative packaging. These findings contribute empirical evidence to the discourse on sustainable food systems, emphasizing the practical effectiveness and economic viability of advanced packaging technologies.

Soft-template-assisted bottom-up fabrication of tunable porosity monolithic copper film for interconnection in microelectronics

Background: Third-generation devices offer superior attributes, necessitating advanced packaging materials for harsh operating environments. Incorporating 3D porous architectures to increase the reaction area further enhances the reaction rate, making transient liquid phase bonding an ideal interconnection process. Methods: Fabrication of monolithic porous Cu films using a bicontinuous microemulsion (BME) as a dynamic soft template is reported. The BME phase consists of interconnected three-dimensional networks of aqueous and oil phases, separated by surfactants and cosurfactants. This unique structure enables the selective electrodeposition of Cu exclusively within the aqueous region, preventing any unwanted reactions in the oil phase. Tunable porosity in the monolithic Cu film is achieved by adjusting the water to oil phase ratio in the BME. Significant findings: The Sn-plated porous Cu films exhibit low-temperature reflow capability while still maintaining high service temperatures. The utilization of the BME soft template offers a promising approach for fabricating monolithic Cu films with tunable porosity, providing flexibility in controlling the compositions and performance of interconnections. The compatibility of the BME with existing wafer deposition techniques makes it a viable and scalable solution for mass production. The electrodeposition of monolithic Cu arrays on Cu pillars demonstrates its potential applicability in advanced packaging technologies.

Freeze Frame Reflow to Enhance Yields for Advanced Low-Profile Bottom Terminated Packages

Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more circuit board real estate toward end-user applications – all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required. Unlike most gull wing style leaded packages, QFNs (Quad Flat Pack No lead packages) also known as BTCs (Bottom Terminated Components) have coplanar terminals below the package body to answer this ever-decreasing form-factor requirement. The final standoff in these QFN style packages are dictated by the solder joint geometry formed. Within this advanced package family also finding a similar trend are power WCSPs (Wafer Chip Scale Packages) where traditional solder spheres are being replaced with low profile interconnects in expanded and asymmetrical geometries. This paper presents factors that influence advanced low standoff package solderability performance with the use of video microscopy and live in situ X-ray reflow. To reflect the QFN board assemblies that are typically designed a series of layouts were implemented across different coupon test boards. Assembled coupon test board were designed by varying 1) through hole via design, 2) solder mask tenting techniques, 3) periphery and center thermal pad printed solder joint volumes, 4) no-clean and water-soluble solder paste flux chemistry all using SAC 305 alloy and type 4.5 powder size. One case study using live in-situ X-ray system will explain the effects of a QFN land pattern layout incorporating vias in the center thermal pad with solder mask tenting over the via openings located on the back of the PCB. In another configuration vias were removed from the center thermal pad and vacuum reflow performed during the liquidus phase of the solder with an explanation of why some of the voids remained. The first and second order results presented within this paper have practical implications and from their observations a novel process evaluation technique coined as Freeze Frame Reflow (FFR) was developed. In the last case study presented, an advanced mrQFN (multi-row QFN) package is investigated for factors affecting yields. FFR is then implemented resulting in an increase in yield further demonstrating the benefits this new & novel technique can offer.

A strategy to prepare low-temperature curable photosensitive polyimide with good comprehensive performance

Low-temperature curable photosensitive polyimide (PSPI) materials have attracted widespread attention in advanced packaging, serving as key insulating dielectric materials in redistribution layer (RDL) to avoid wafer warpage. Considering PSPI and copper together formed the core RDL part, the adhesion between PI and copper need to be concerned to realize high reliability. However, the exploration of novel diamines with desirable characteristics such as low temperature curing ability, improved adhesion and excellent lithography properties was limited. We designed a new diamine with fluorine-containing pyridine side group named PyFNH2, which facilitated preparation of low-temperature curable polyimide (at 200 °C) with remarkable degree of imidization (≥95.9 %). Secondly, the coordination interaction between pyridine side group and copper enhanced adhesion strength. Thirdly, the PI films cured at 200 °C exhibited favorable dielectric properties compared to control films without PyFNH2, because of the introduction of electronegative fluorine atoms and rigid side groups. Apart of these, the PI films possessed fairly good thermal and mechanical properties. Significantly, negative-tone PSPI employing the precursor poly (amic ester) with PyFNH2 was successfully prepared and cured at 200 °C, enabling precise lithography patterns with line resolutions down to 3 µm. Our findings highlight promising application potential of PyFNH2 in photolithography technology, offering a feasible strategy for structure designs of low-temperature curable diamine.

Facile Synthesis and the Thermal Properties of Al/Si Composites Prepared via Fast Hot-Pressing Sintering

In this paper, a novel power sintering technique, named fast hot-pressing sintering (FHP), which is able to achieve an ultrahigh heating rate similar to the spark plasma sintering (SPS) technique, but at a much lower cost, was applied to prepare a series of Al/Si composites with different Si volume ratios (12 vol.% to 70 vol.%) to meet the requirements of advanced packaging materials for electronic devices. In contrast to SPS, the FHP oven possesses a safe and budget-friendly current power supply, rather than a complex and expensive pulse power supply, for its heating power. The optimized sintering parameters (temperature, pressure and holding time) of FHP for preparing Al/Si composites were investigated and determined as 470 °C, 300 MPa and 5 min, respectively. In order to characterize the potential of Al/Si composites as packaging materials, thermal conductivities and coefficients of thermal expansion were studied. The thermal conductivity of the Al-40Si composite sintered by the FHP method is higher than that of the conventional SPS method (139 to 107 W m−1 K−1). With the increase in Si, the thermal conductivities and coefficients of thermal expansion on both decreases. Furthermore, the thermal conductivities obey the Agari model, whereas the coefficient of thermal expansion and Si volume ratios obey additivity. The numeric modeling would help develop required packaging materials based on the thermal performances of the substrate materials, like Si or GaAs semiconductor devices.

Cutting speed dependence of material removal mechanism for monocrystal silicon

In advanced semiconductor packaging, silicon wafers are typically thinned to tens of microns in thickness using ultra-precision grinding techniques, and the cutting speed greatly determines their surface integrity. However, an in-depth understanding of fundamental material removal mechanism considering the strain rate effect has not been revealed yet. This paper systematically explores the impact of cutting speed on the penetration depth, subsurface damage characteristics and scratch-induced stress field for monocrystal silicon material. First, nanoscratch tests in varied-load and constant-load modes are performed under different scratch speeds on the silicon specimen surface. The surface morphology of generated groove is observed to identify its brittle and plastic features. Next, the geometric relationship and contact pressure between the indenter and workpiece during the scratching process are analyzed. A theoretical penetration depth model is developed considering scratch speed, indenter tip radius and elastic recovery. The corresponding parameters are solved via the particle swarm optimization algorithm and agree very well with the experimental data. Then, the subsurface damage under different scratch speeds is measured by a transmission electron microscope. The atomic scale lattice defects are presented, involving the amorphous layer, stacking faults and phase transformation. Finally, a scratch-induced stress field model is established to interpret the distortion degree variation in damaged regions with scratch speed. The distribution of stress components in the scratch region is presented.

Synthesis of poly (amic ester) with controlled molecular weight for photosensitive polyimide in advanced package

Photosensitive polyimide (PSPI) with excellent lithography patterning and superior comprehensive properties have emerged as a very promising material for the advanced electronic package in IC field. Thereinto, poly (amic ester) (PAE) with highly sensitive groups and suitable molecular weight becomes the most important component in PSPI. Herein, a series of PAEs are synthesized by 4,4-oxydiphthalic anhydride, 4,4′-oxydianiline, and 2-hydroxyethyl methacrylate. The molecular weight of PAE was carefully controlled by using phthalic anhydride as the end-capping agent ranging from 9 000–20 000 g/mol. With the cooperation of photoinitiator and crosslinker, high-performance PSPIs were obtained. The results showed that the PAE with a molecular weight of 15 000 g/mol showed the best performance of lithography with resolution of 10 µm. The further increase of the molecular weight resulted the residues after developing, while lower molecular weight exhibited partially imidization during the pre-baking process, leading to a decrease in the solubility of PAE, as well. Additionally, as-prepared PSPIs also performed excellent thermal, mechanical, and dielectric properties, showing tensile strength of 120 MPa, elongation at break of 8%, glass transition temperature and the temperature of 5% weight loss of 260 °C and 430 °C, respectively. All these results exhibit a great application potential for high performance advanced packaging.

Copper Sintering Pastes with Various Polar Solvents and Acidic Activators.

Devices in the developing semiconductor market require high density, high integration, and detailed processing. Conventional wire bonding is inappropriate for fine-sized devices, and connected wires can be damaged by heat generation and external physical impact. Soldering is also used in advanced packaging technologies. However, disturbances and overhead joints can occur during bonding. Thus, sintering has been extensively utilized to overcome these drawbacks. Sintering pastes are pressurized and bonded, resulting in stable bonding during sintering. In this study, the composition of the Cu sintering material was examined using diverse additives and solvents. We manufactured sintering materials comprising Cu (1 μm), a solvent [methanol (MeOH), ethanol (EtOH), or ethylene glycol (EG)] and an acidic additive (benzoic acid, phthalic acid, or hexanoic acid). After the sintering process, the mechanical and electrical characteristics were compared to determine the optimal composition and bonding conditions. The optimum ratios between the acid and solvent were 4:6 (MeOH and EtOH) and 2:8 (EG) due to the high viscosity and effective long-term storage. All samples using EtOH as the solvent exhibited the highest sintering performances. The aromatic and carboxylic groups substantially improved the sintering performance and increased the electrical conductivity. Based on the O1s/Cu2p ratio (2.23%), the best sintering composition was EtOH/PA, which showed the highest electrical conductivity (ca. 104 S/m) and strength (34.0 MPa). The sintering process using various additives and solvents can be helpful to determine the sintering conditions while maintaining the electrical properties.

Oriented design of wafer-level stacking structures to enhance reliability of laser debonding of thin devices

The laser debonding process in advanced packaging has become a key technology for the debonding of ultra-thin wafers. However, improving the reliability of debonding and efficient removal of adhesive residues from thin and brittle devices remains challenging. Here, we fabricated bonding pairs formed by inorganic responsive layer, thermal buffer layer, and adhesive layer based on a structural design-oriented strategy. Experimental results showed that the thinned device wafers did not show any damage after laser debonding, and the residual adhesive film could be easily torn off. The response layer (a-Si:H) with high temperature resistance and corrosion resistance has strong photosensitivity under the action of ultraviolet laser with a wavelength of 355 nm, and rapidly decomposes to release H2 and polysilicon nanoparticles. The thermal buffer layer is primarily intended to block the heat flow and compensate internal stress. The adhesive layer acts both as an adhesive during temporary bonding and as a barrier to laser-induced gas shock waves and plasma etching of device layers during debonding. This rational structural design contributes to improves the reliability of the laser debonding process and shows great potential for application in the next generation of thin device debonding.

Supramolecular cross-linking affords chitin nanofibril nanocomposites with high strength and water resistance

Polysaccharide nanofibrils of chitins or celluloses are emerging biobased building blocks for sustainable, high-performance bioinspired nanocomposites fusing high stiffness, strength, and other functionalities. Owing to their hygroscopicity, a crucial challenge towards real-life applications of these nanocomposites is to maintain their mechanical performances in the humid or even fully swollen conditions. Here, we report water resistant nanocomposites composed of sustainable chitin nanofibrils (ChNFs) and polyvinyl alcohol (PVA) that are physically cross-linked by tannic acid (TA) to enhance and stabilize wet mechanical properties. We demonstrate that the formation of polymer-coated core/shell nanofibrils at the intermediate stage is crucial for the well-defined nanopaper structures after casting. By infiltrating TA, the formation of hydrogen bonding in the PVA matrix and at the ChNF/PVA interface renders the nanocomposites with extremely high strength and stiffness, even under high humidity and swelling conditions. With the increase in the amount of conjugated TA, the Young's modulus and tensile strength of the swollen nanocomposites reach up to 3.0 GPa and 70 MPa, respectively, which are superior to the existing water-borne nanofibils/polymer nanocomposites. Moreover, the nanocomposite films show excellent gas barrier properties at high relative humidity (90%), as well as UV shielding, antibacterial properties and biodegradability, complementing the multifunctional property profile and allowing a transfer into applications as advanced packaging materials.