Heterogeneous Integration with 3D Packaging

Abstract

The next generation of competitive integrated devices demand increased device density, higher memory bandwidth, reduced global interconnects, increased energy efficiency (with higher performance), and a smaller footprint. With the slowdown in Moore’s law and the advancements in chiplet architectures, which are now recognized as fundamental to enabling the continued economically viable growth of power efficient computing, advanced packaging technologies and architectures are becoming more critical to enabling Moore’s Law’s next frontier through heterogeneous integration. In this presentation, we will cover the advanced package architectures being enabled by AMD to enable power, performance, area, and cost (PPAC) improvements as well as enable heterogeneous architectures. The direct Cu-Cu bonding technology used in AMD 3D V-Cache architecture will be detailed and compared to industry standard 3D architectures.