Abstract
Heterogeneous chiplet integration has become a crucial performance enabler in the microelectronics industry by providing the flexibility of die disaggregation, and the ability to mix/match different IP blocks optimized on different Si nodes in a single package. It shows great potential in supercomputing, autonomous driving, artificial intelligence, and machine learning applications. With rising demand in high performance computing, the key focus in heterogeneous integration (HI) scaling has been to push interconnect density with increased bandwidth and improved power efficiency. In this paper, we provide an overview of embedded multi-interconnect bridge packaging technology scaling and discuss key considerations for advanced substrate packaging technologies to enable further HI applications.
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