Influence of Rigid Carrier Substrates & its Release Layer on Ultra Fine Pitch chip last FO-WLPs

Abstract

In recent years the leading-edge product enablers in Wireless Connectivity for WiFi & Bluetooth, Wearable HD Modules, Artificial Intelligence (AI), Application Processors etc. require ultra-high density chip packaging device using heterogenous integration to constructing the SiP modules. In order to meet their requirements, fan-out chip last WLP – having its redistribution layer (RDL) constructed first – is definitely the solution of choice to assemble devices in such advanced packaging platforms. This approach further eliminates known good die (KGD) loss risk, resulting in higher assembly yield and lower cost. Rigid carrier substrate and the release layer placed on top of it influences the process yield of fan-out chip last WLP. It gets more challenging when ultra-fine pitch redistribution layers (RDL) are required. This paper focuses on the influence of release layer on quality of narrow line & space RDL, as well as on the separation force during debonding. It further describes an optimized solution through HRDP® (High Resolution Debondable Panel) technology, which is the most compatible carrier to fabricate the leading-edge fan-out chip last process. The HRDP® carrier is offered in various dimensions and thicknesses as round wafers and square/rectangular panels with glass or silicon to match customer requirements. This is made of 100% inorganic material, which helps to improve interfacial stresses and facilitates debonding. During processing, this inorganic release layer (IRL) demonstrates higher chemical resistance and heat resistance than alternative technology such as the laser lift-off (LLO) type carrier.