Addressing Challenges in Dual Sided SiP Thermal Budget

Abstract

System-in-Package (SiP) has been adopted as the mainstream advanced packaging technology in many consumer applications including 5G smartphones, tablets, wireless earbuds, smart wearables, etc. Heterogeneous integration, smaller form factor, better electrical performance, lower cost of assembly and faster time to market are the key differentiators of SiP as compared to conventional packaging techniques. In applications such as 5G mobile RF Front-End (RFFE) and Antenna-in-package (AiP) modules, dual sided SiP is the popular approach which brings even higher level of integration and smaller form factor. However thermal warpage control is a significant challenge during two times of solder reflow processes for the front and back sides of the package, especially if one side is with underfill and mold materials which have significant CTE mismatch to the substrate and dies, causing delamination failures and yield losses. This study examines the novel solution of reducing thermal budget with the use of a low temperature solder paste material based on SnBiAg alloy in ultra-fine pitch Type 6 solder powders. It allows a minimal peak reflow temperature of only 170 °C that effectively reduces warpage of dual sided SiP substrates. Solder alloy and paste properties and solder joint microstructures are examined in detail for tests including fine-pitch printing and component soldering, thermal aging test on different substrate finishes, thermal cycling test and mechanical drop test for reliability performance.