Adders In Terms Research Articles

Design of High-Speed Area-Efficient VLSI Architecture of 32-Bit Three-Operand Binary Adder

Abstract: Adders are one of the most widely used digital components in digital integrated circuit design. With the advances in technology, the design that offers either high speed, low power consumption, less area, or a combination of them is designed. There are various processes performed by the digital circuits among which arithmetic operations are prominent. Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the three-operand addition. However, the ripple carry stage in the CS3A leads to a high propagation delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson (HCA) can also be used for three-operand addition, significantly reducing the critical path delay at the cost of additional hardware. Hence, a new high-speed and area-efficient adder architecture is designed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area, low power, and drastically reduces the adder delay. To design a faster computing system with less hardware we require some other architecture. The proposed architecture will reduce the area as well as the delay by replacing the Han-Carlson adder with the Ladner fisher adder in a Highspeed area-efficient three-operand binary adder. The proposed architecture is synthesized with the zynq-7000 library. The proposed architecture reduces the LUT count and delay by 20 and 0.4 nanoseconds respectively. By using these synthesis results, we noted the performance parameters like the number of LUTs and delay. We compared the adders in terms of LUTs (represents area) and delay value

Performance Analysis of Notch Filter in ECG Signal Noise Reduction

An electrocardiogram (ECG) is a medical test that records the normal and abnormal condition of the heart. It is an essential tool for identifying vari- ous cardiac related issues. However, ECG wave are often distorted by diverse noise sources, such as movement artifacts or electrical interference. To remove these artifacts and enhance the quality of the ECG signal, various filters are commonly used. The choice of filter type depends on the definite necessities of the application. FIR filters are used in the area that needs linear time response and accurate amplitude response. They have a stable and predictable response and are more robust to coefficient quantization errors. However, they require a larger number of coefficients to achieve the desired frequency response, which can lead to increased computational complexity. The use of digital filters, specifically notch filters, for denoising ECG signals is an effective technique. Adders are essential components in the design of notch filters, and researchers have been exploring different types of adders to improve the parameters of these filters. In this paper, the Ripple carry adder, Carry select Adder, and adder using Carry skip are compared in terms of their performance parame- ters, including area, delay, and power consumption. The RCA is a basic adder, while the C-Skip and C-Select adder are designed to reduce the delay of the addition operation. The results of the study showed that the C-Skip and C- Select adder outperformed the R-Carry adder in terms of delay and power con- sumption. The C-select adder had the lowest delay, while the C-Skip adder had the lowest power consumption. However, the area of the C-select Adder was larger compared to the other adders. Overall, the selection of adder depends on the particular need of the application. Notch filter used for ECG noise removal designed using these adders and its performance is analyzed.

High-Performance 10-Transistor Adder Cell for Low-Power Applications

Addition is one of the most fundamental arithmetic operations. Any adder in a digital circuit and system can improve the digital system's performance. Adders, for example, are commonly found in the critical path of many ALUs, processors, and digital signal processing chips. As a result, each of these blocks should execute efficiently and precisely on their own, enhancing the overall performance of the system. Optimizing an adder may lead to overall system optimization. A desirable adder meets all the criteria, such as high speed, low-power dissipation, low leakage power, and small footprint. However, because there is a trade-off between the area, power and, speed.Obtaining the finest adder in terms of speed, power dissipation, leakage power, and area consumed would assist the designer in selecting an adder for the given application. Transmission function adder (TFA), 17-transistor adder (17-TA), 14-transistor adder (14-TA), ripple carry adder (RCA), carry lookahead adder (CLA), and carry-select adder are among the new 2-bit adders suggested and compared (CSL). This research presents a comparative analysis and performance evaluation of adders based on latency, power dissipation, PDP, leakage power, area, and EDP. Simulations are being done using HSPICE software at 28-nm technology with a supply voltage range of 0.7–1.1 V. The suggested adder has a minimum delay and is 8.6% faster than CLA, according to simulation results. When compared to the other adders, it uses the minimum area and has the lowest leakage power. The proposed adder has minimum power delay product.

Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders

In this paper we analyze, design and compare six significant topologies of one-bit full adders in terms of their Energy-Efficient Curves in the Energy-Delay Space.We define the simulation strategies that are adopted to make a fair comparison even among cells with very different characteristics. Each topology is designed through a methodology which, thanks to the adoption of a circuit optimizer, allows to design the circuit under different energy-delay trade-offs and to derive the Energy-Efficient Curves. The comparison of the topologies is made using a 28 nm CMOS technology in terms of normalized Energy-Efficient Curves. In particular, plotting all these Energy-Efficient Curves in a single graph makes the comparison very effective and allows the designer to choose the best topology or discard the worst ones, at a glance.

Low energy, long sustainable and high-speed FIR filter based on truncated multiplier with SCG-HSCG adder

In advancement technology and applications like processing sound signals, processing image signals, software define radio signals and so on. In processing of digital systems in all type of devices may be wide range of contraptions and clamors. The result of design the all the athematic devices and performing the addition and multiplication operations need larger space in very large scale implementation. Here, the latest proposed methodology progressed in the design of Finite impulse response filter by redesign the multipliers and adders to introduce new unsigned and signed truncated multiplier and new SCG-HSCG adders. Also different III-Vth semiconductor materials can be used to get high speed filtering operation. In this way to decreases the partials part reduction of design truncated multiplier have more number of adders. The new design handles to replace the SCG-HSCG Adders. This design decreases the logic gates in operations of athematic, additions and multiplications. It also gives the more efficient in the sign and unsigned designs of different digital signal processing applications. This proposed new finite impulse response filter has designed with help of VHDL and Xilinx FPGA-S6LX9. The efficiency of proposed filter with truncated multiplier and SCG-HSCG adder, is compare with the existing all CSLA – Carry Select adder in terms of area, delay, and power. The novel FIR filter design reduces power distribution to the environment while increasing hardware device performance. Furthermore, these kinds of designs take up less space, which means they use less energy and last longer.

Performance Analysis of High Speed and Low Power Binary Adders

In all the arithmetic operations, addition is one of the most important and initial operations used in most of the mathematical equations. The operation is performed by many adders present in the digital world. These adders give us carries with preferred delay and power. The three main features like structure, logic, and compact circuit layout help design a better adder. This Paper aims to analyse and compare various additions for high-speed, low-power and fast calculation. The various adder designs seen in digital signal processing applications require computationally efficient adding and cumulative operations, so blocks with the required attributes must be carefully selected. Various techniques have been proposed to design efficient adders in terms of performance, low power consumption and area. This work focused on 16-bit implementations of highly optimized area-efficient Ripple Carry Adders (RCA) and Look Ahead Carry Adders (LAC), and carry select Adder. Finally, we can prove that the Carry look ahead Adder is very fast in all existing designs. These processes are simulated and synthesized in all ISE Xilinx 14.7 software.

Ultra-Low Power 8-Transistor Modified Gate Diffusion Input Carbon Nano-Tube Field Effect Transistor Full Adder

An ultra-low power 8-Transistor Modified Gate Diffusion Input (MGDI) Carbon Nano Tube Field Effect Transistor (CNTFET) Full Adder (FA) has been presented in this paper. The proposed 8-T MGDI CNTFET Full Adder outperforms other adders in terms of Power Consumption, Propagation Delay and the PDP at different levels of Power Supply and Temperatures. The power consumption of the proposed 10 nm CNTFET 8-T MGDI Full Adder at 27°C is 1.96 nW. The proposed CNTFET FA exhibits 60.32% improvement in Power Consumption when compared to the existing 10 nm FINFET 8-T MGDI Full Adder. The propagation Delay of the proposed FA is 42.16 ps and an improvement of 57.68% is noticed over the existing FA. The Power Delay Product of the proposed 10 nm CNTFET 8-T MGDI FA is 82.63 × 10−21 Jules, whereas the PDP of the 10 nm FINFET 8-T MGDI FA is 492.07 × 10−21 Jules. The PDP of the proposed 10 nm CNTFET 8-T MGDI Full Adder exhibits 83.21% improvement when compared to the 10 nm FINFET 8-T MGDI FA.

Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder

Background: Full adder is the key element of digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder, CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with a new Gate diffusion technique has been implemented in this work. This is a comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultra-low-power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit. Moreover, it also reduces the number of transistors required. This technique has been used with CNTFET to upgrade the full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The FinFET design also shows the better performance with GDI. But GDI enhances CNTFET based design power consumption by about 32% from the FinFET. Conclusions: CNTFET showed a better response due to good current conductivity as compared to the FinFET. This work has been implemented and simulated on the 32nm node technology.

Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders

In recent years, approximate circuit design targeting the error-tolerant applications has gained significance. In this study, the authors propose a metric that ranks a stand-alone approximate adder in terms of power savings obtained for a given mean error distance/mean square error (MSE). The authors demonstrate that this ranking of approximate adders can be used in applications that contain adder trees and registers. In applications that also have accurate multipliers interspersed with adders, the authors find that certain types of approximations in the adders result in more power-efficient implementations of multipliers. Besides power savings, the other metrics of interest are noise floor and mean error in filtering applications and the compression achieved for a given peak signal-to-noise ratio (PSNR) in image compression applications. The authors also show that for the same overall MSE, there is a trade-off between noise floor and mean error. This makes it possible to classify these adders based on whether they result in an increased noise floor or a mean error for the same overall MSE. Furthermore, the authors discuss the effect of using an approximate discrete cosine transform block to meet the reduced PSNR requirements, on the overall compression levels and the trade-offs involved in the process.

Realization of Various Topologies of Adders Based on H-Dycml

Power consumption minimization in a circuit becomes imperative with growth in demands of portable goods. However, at the same time, its speed limits the performance of a system. Therefore, there is a need of choosing optimum circuit architecture that takes into account the both conflicting parameters, that is, power dissipation and speed. Arithmetic unit is one of the vital components of portable goods and out of all arithmetic operations, adders are the most commonly used. To address the issue of high power dissipation, low-power designing styles are becoming prominent now-a-days. Hybrid Dynamic Current Mode Logic is high-speed, low-power designing style that has been recently proposed in literature. Therefore, this paper presents the comparison between performances of various topologies of adders that are implemented using a high-speed, low-power designing style: Hybrid-Dynamic Current Mode Logic (H-DyCML). All the circuits are realized in Cadence Virtuoso using 180nm CMOS technology parameter. Various performance parameters are evaluated such as: Delay, Power, Power-Delay Product, and hardware utilization. It is found that carry look-ahead adder out-stands other adders in terms of overall performance.

Design and Implementation of Full Adder using Different XOR Gates

A Full Adder is a logical circuit that servers a great part in the design of application particular integrated circuits. It is the basic component found in VLSI and DSP applications. The applications of Full adder in VLSI include ALU design, Address generation in processors, Multipliers and so on. Power consumption is one of the most significant parameters of full adder. Therefore, reducing power consumption in full adder is very important. In this paper, Design XOR gate using Transmission gate logic (TGL), Pass transistor logic (PTL) and Static Complementary metal oxide semiconductor logic (CMOS). Also design Full Adder circuit using different XOR gate designs. These circuits are designed and implemented, simulated using Mentor Graphics Tool. After getting simulation results, compare the different XOR gate designs based full adders in terms of power consumption and delay. Using the comparative analysis for the designed Full Adders, an effective adder design can be chosen based on the performance criteria as required by the designer.

Low power and area efficient error tolerant adder for image processing application

SummaryApproximate computing‐based arithmetic units are oriented towards reduction in power, delay, and area. Intrinsic error tolerance capability of emerging application domains, like multimedia, Internet of Things (IoT), and image processing provides better opportunities for optimization of approximate arithmetic units. In this paper, a novel 1‐bit imprecise full adder (IFA) is proposed with less gate count. Also, two versions of 16‐bit error tolerant adders (ETAs), namely a low power and area efficient error tolerant adder (LETA) and improved low power and area efficient error tolerant adder (ILETA), are proposed. In these proposed ETAs, the most significant bit (MSB) segments are realized in same approach, whereas the least significant bit (LSB) segment of LETA and ILETA are realized using an existing modified full adder (MFA) and proposed IFAs, respectively. The proposed and existing ETA adders are implemented using a Verilog hardware description language (HDL) and synthesized in a Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65nm technology. The proposed (ILETA, LETA) adders exhibit (55%, 50%) reduction in power consumption and achieve significant reduction in area (68%, 61%). Further, in this work, a new performance metric namely power and error product (PEP) is proposed in order to evaluate the approximate adders in terms of power and error metrics. It is found that the proposed ILETA achieves a low PEP of 1.05 compared with other ETAs. To study the efficacy of the proposed ETA adders in image processing application, an image blending algorithm is implemented and simulated using MATLAB. From simulation results, it is observed that the proposed ETA adders exhibit a high peak signal‐to‐noise ratio (PSNR).

Low Voltage Full Swing Fin FET Hybrid Full Adder

In this research paper, CMOS and FinFET based hybrid Full Adders operating at low voltages with low power dissipation are proposed. The proposed CMOS based circuit is compared with few existing hybrid full adders in terms of average power dissipation and power-delay-product (PDP). The designed CMOS based hybrid adder achieves lower power dissipation and low PDP compared to other hybrid adders over a voltage range of 0.6V to 1V. The proposed CMOS implementation of hybrid full adder fails at 0.5V to produce full swing output. To solve this full swing problem, the proposed hybrid full adder is implemented using FinFETs which produce full output voltage, lower power and low PDP comparing with CMOS implementation. The circuits are designed with HSPICE tool in 32nm predictive technology model (PTM).

Faster Carry Bit Computation for Adder Circuits with Prescribed Arrival Times

We consider the fundamental problem of constructing fast circuits for the carry bit computation in binary addition. Up to a small additive constant, the carry bit computation reduces to computing an A nd -O r path, i.e., a formula of type t 0 ∧ ( t 1 ∨ ( t 2 ∧ (… t m −1 ) …) or t 0 ∨ ( t 1 ∧ ( t 2 ∨ (… t m −1 ) …). We present an algorithm that computes the fastest known Boolean circuit for an A nd -O r path with given arrival times a ( t 0 ), …, a ( t m −1 ) for the input signals. Our objective function is delay, a natural generalization of depth with respect to arrival times. The maximum delay of the circuit we compute is log 2 W + log 2 log 2 m + log 2 log 2 log 2 m + 4.3, where W := ∑ i = 0 m −1 2 a ( t i ) . Note that ⌈ log 2 W ⌉ is a lower bound on the delay of any circuit depending on inputs t 0 , …, t m −1 with prescribed arrival times. Our method yields the fastest circuits for A nd -O r paths, carry bit computation, and adders in terms of delay known so far.

An Efficient Module for Full Adders in Quantum-dot Cellular Automata

Quantum-dot cellular automata (QCA), a new computing paradigm at nanoscale, may be a prospective alternative to conventional CMOS-based integrated circuits. Modular design methodology in QCA domain has not been widely investigated. In this paper, an efficient module with fault tolerance is proposed, which can be employed to fabricate three-input and five-input majority gates that are the fundamental primitives for designing circuits in QCA. With cells omission in the versatile module, various logic gates will be achieved, such as Nand-Nor-Inverter (NNI) gate and And-Or-Inverter (AOI) gate. Moreover, in order to seek out an efficient full adder, five various QCA full adders are designed and exhaustively compared in terms of area, complexity, latency, reliability and power dissipation and also compared with existing fault-tolerant full adders. Two simulation tools, QCADesigner and QCAPro, are utilized in the waveform simulations for verifying the correctness of proposed circuits and power consumption, respectively. The analysis results reveal that full adder V has significant improvements in contrast to its counterparts with above criteria. To test the practicability of full adder V, multi-bit adders will be designed in single-layer and compared with previous adders in terms of area, complexity and QCA cost, which proves the merits of our work.

High Speed Error Tolerant Adder for Multimedia Applications

In this paper, a 1-bit modified full adder (MFA) cell is proposed. This eliminates the carry propagation during the addition by allowing errors in the carry bit. Using the proposed MFA, a 16-bit high speed error tolerant adder (HSETA) circuit is designed with conventional carry select adder (CSLA) structure for higher order bits and MFA based structure for lower order bits. The performance of HSETA is compared with existing adders in terms of accuracy, gate count, delay and power dissipation. The gate count of the HSETA is reduced by 23% and speed is improved by 43% compared to a conventional 16-bit adder structure. Further, implementation on FPGA Spartan 6 shows that HSETA uses 53% fewer LUT and 63% fewer slices compared to the conventional adder. Image blending application is used to evaluate the performance of the HSETA. In addition, to perform extensive error analysis, an analytical model is developed for HSETA and tested for varying bit widths and input probabilities. The analytical model is validated through simulation.

ENGLISH

Arithmetic and memory address computation are performed using adder operations. Hence, design of adders forms an important subset of electronic chip design functionality. BCD numbers play a prominent role in number system. To perform arithmetic operations on BCD numbers respective circuit has to be designed. To perform BCD addition, BCD adders are used. But the drawback with the BCD adder is low speed in operation due to delay in propagating carry output. This low speed operation will affect the operation of entire system in which it is used. As the technology is advancing day by day there is demand for chips with high speed. So to overcome this drawback, BCD adder using CLA is proposed in this paper. The proposed design is attempted here to reduce the delay and thereby increasing the speed of response. In existing BCD architecture, RCA is used to add numbers. The delay of RCA is high so it is effecting the speed of adder. So in the proposed design, CLA is used instead of RCA and also a parallel prefix network is to be used to produce the carry outputs for all stages. In this paper, a BCD adder using CLA is to be designed for 8, 16, 32, 64 and 128-bit size using VHDL with the help of ISE Xilinx design suite 14.1. The designed adder will be functionally verified by using ISIM simulator. Later, it will be synthesized using XST synthesizer to get the area (in terms of LUTS) and delay(ns). Finally, the designed BCD adders will be compared with conventional BCD adder in terms of delay(ns).

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

Prodigious demand for fast performance-ultra low power electronic devices has insinuated the discovery of circuit style that promises reduced propagation delay (t p ), as well as low power dissipation (PWR). MOS current mode logic (MCML) style has emerged as a promising logic style that offers high speed of operation at the expense of acceptable power dissipation. This paper proposes a MCML full adder which employs a load controller circuit. It compares MCML full adder with hybrid-CMOS full adder in terms of various design metrics in superthreshold as well as subthreshold regions. MCML topology with load controller offers a high speed of operation and low power dissipation in superthreshold region. Same circuit arrangement, when operated in subthreshold region also delivers higher operating speed with ultralow power dissipation compared to its hybrid-CMOS counterpart. Power dissipation analysis established MCML based full adder more robust compared to its hybrid-CMOS counterpart. In particular, MCML full adder design achieves 3.77× (2.38×) improvement in propagation delay, 10.43× (3.45×) improvement in average power dissipation, 39.43× (8.21×) lower power-delay product (PDP) and 149.07× (19.55×) improvement in energy-delay product (EDP) in superthreshold (subthreshold) regions of operation at 16-nm technology node. The above results are also validated using TSMC’s industry standard 0.18-μm technology model parameters and a similar trend is observed in the design metrics of the MCML and hybrid-CMOS full adder circuits. In addition, noise performance of the above mentioned circuits is also carried out. It is observed that the noise induced by the hybrid-CMOS full adder is about 14× to that of the MCML full adder.