16-bit Multiplier Research Articles

Low power, high speed approximate multiplier for error resilient applications

This paper proposes novel constant carry-based approximate compressors for partial product reduction in the binary multiplier. The constant carry compressors have only Sum as output and the output carry bits are either constant 0 or 1 and hence no requirement of logic computation. This will evidently remove the carry chain when these compressors are utilized for column reduction in multipliers. This work examined the 4-bit multiplier with two different constant carry chains (Type-1, Type-2) since there is possibility of two constants. The 8-bit multipliers are built using 4-bit recursively with both the types. By analyzing the two modes, it is concluded that Type-1 i.e., constant carry chain of all zeros is efficient in terms of error and energy. The existing best design of approximate compressor based multipliers (M1, M2) of Ansari et al. (2018) are compared with proposed multipliers. The proposed 8-bit multipliers of either Type-1 or Type-2 work with the maximum delay of 245ps, whereas the existing designs work with maximum delay of 300ps. The proposed designs have constant delay and also nearly 40% energy savings for increase in ER of 2% and the MED increment of 0.72, 3 when compared to M1 and M2 designs respectively. The proposed multiplier effectiveness is demonstrated using image smoothing, edge detection, and Discrete Cosine Transform (DCT), resulting in high acceptable values for quality metrics of Average PSNR, SSIM, and PIQE. The PSNR for DCT is 28 dB with SSIM of 0.99 and PIQE of 42.9.

Implementation of multiplier using Vedic mathematics

Every digital circuits need processors. Every processor performs arithmetic and logical operations. There are four arithmetic operations out of which multiplication is one of the main operation. To perform multiplication, multipliers are used. Various algorithms are used to implement multipliers. Vedic algorithm is one of the algorithm and is designed using ancient Vedic sutras. In this paper design and implementation of 4-bit vedic multiplier is done and the results are compared with 4-bit array multiplier. From the result it is observed that 4-bit vedic multiplier is efficient in terms of speed. There are 16 sutras out of these URDHVA TRIYAGBHYAM sutra is used to decrease the delay of the multiplier. This is designed using Cadence tool 45 nm technology.

High-speed pre-accumulator and post-multiplier for convolution neural networks with low power consumption

In today's phase of growing technology Convolution Neural Networks (CNNs) are all over the places. It is a thriving segment in machine learning and Artificial Intelligences (AI) techniques. CNN needs bulk amount of computing competence and memory with higher frequency range. In this present investigation, Pre-Accumulator and Post-Multipliers (PAPM) are proposed which accelerate the speed of processor. 4-bit multiplier using Carry Save Adder (CSA) is built with 6Transistors-Adder and sutras of Vedic mathematics is constructed. Accumulator of multiplier and accumulator are designed with Two Level Edge Triggering Flip-Flops (TLET-FF) to increase bandwidth of the memory. The proposed architecture of Multiply Accumulate (MAC) circuit consumes very less power when compared to existing high speed MACs. Performance of accumulator is contrasted with three different, two-level triggered flip-flops namely 16TLET-FF, 14TLET-FF and 12TLET-FFs. The projected MAC replaces the existing multipliers due its low power together with high frequency of operation.

Arithmetic and Logic Circuits Based on ITO-Stabilized ZnO TFT for Transparent Electronics

In this paper, general logic cell and module designs in basic digital signal processing (DSP), for transparent, flexible chips and wearable electronics are presented. Modified Circuits from ratioed logic and pass transistor logic styles are modified and proposed, based on n-type-only indium tin oxide (ITO) stabilized ZnO thin-film transistors (TFTs) process. Elaborations on logic circuits with purely n-type TFT transistors were carried out to extend the logic swing of circuit outputs and accelerate the signal propagation in complex logic functions with simplified pull-up/pull-down or passive networks. To implement logic complexes on multiple OR-of-ANDs functions with better performance, tailored active controlled ratioed logic style is adopted with faster speed and smaller area by simplifying the transistor networks properly. All the circuits were fabricated on transparent glass plate. The featured 2-input/3-input XOR gate, 4-1 MUX and D flip flop (DFF) can operate with maximum featured delays of 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6~\mu \text{s}$ </tex-math></inline-formula> at 5 V power supply, with comparatively over 50% less delays and areas than other state-of-art works. The featured 4-bit adder performs maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16.41~\mu \text{s}$ </tex-math></inline-formula> delay at 5 V in measurement. A 4-bit multiplier is also presented based on the adder and DFF. These proposed TFT circuits exhibited smaller area with relatively moderate-high performance in comparison, which were promising building blocks for transparent flexible DSP electronics with low-speed requirements.

Comparative analysis of 8-bit and 16-bit Array multiplier, modified Booth Multiplier-A Study

Comparative analysis of 8-bit and 16-bit Array multiplier, modified Booth Multiplier-A Study

Development of a device for multiplying numbers by means of FPGA

The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and development of multiplier construction methods, multiplier FIR performance improvement by right-shift and addition method on FPGA (field-programmable gate array) basis. The implementation of MAC-block, hardware implementation of binary multiplier on the basis of multi operand adder, multiplier design by right-sliding and addition with control automaton in the FPGA basis is the actual research tasks presented in a number of papers. The description of features of multiplier implementation, high-speed multipliers with variable bit rate, studies of approaches for designing modular multipliers, FPGA image processing using Brown multiplier for performing convolution operation find application in problems of performance and speed. Also, a number of authors describe implementation of conveyorization method, design of dual multiplier, construction method of 8-bit multiplier with reduced delay, 8-bit high-density systolic multiplier arrays on FPGA and development of high-performance 8-bit multiplier using McCMOS technology. A fragment of a developed device for multiplying numbers is presented in the work by the authors. The principle of operation of a device for multiplication is described. The description of connected elements of the device is given. The timing diagrams of operation of a device for multiplication of numbers are presented.

Energy Efficient Error Resilient Multiplier Using Low-power Compressors

The approximate hardware design can save huge energy at the cost of errors incurred in the design. This article proposes the approximate algorithm for low-power compressors, utilized to build approximate multiplier with low energy and acceptable error profiles. This article presents two design approaches (DA1 and DA2) for higher bit size approximate multipliers. The proposed multiplier of DA1 have no propagation of carry signal from LSB to MSB, resulted in a very high-speed design. The increment in delay, power, and energy are not exponential with increment of multiplier size ( n ) for DA1 multiplier. It can be observed that the maximum combinations lie in the threshold Error Distance of 5% of the maximum value possible for any particular multiplier of size n . The proposed 4-bit DA1 multiplier consumes only 1.3 fJ of energy, which is 87.9%, 78%, 94%, 67.5%, and 58.9% less when compared to M1, M2, LxA, MxA, accurate designs respectively. The DA2 approach is recursive method, i.e., n -bit multiplier built with n/2-bit sub-multipliers. The proposed 8-bit multiplication has 92% energy savings with Mean Relative Error Distance (MRED) of 0.3 for the DA1 approach and at least 11% to 40% of energy savings with MRED of 0.08 for the DA2 approach. The proposed multipliers are employed in the image processing algorithm of DCT, and the quality is evaluated. The standard PSNR metric is 55 dB for less approximation and 35 dB for maximum approximation.

Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration

Low-precision data representation is important to reduce storage size and memory access for convolutional neural networks (CNNs). Yet, existing methods have two major limitations: (1) requiring re-training to maintain accuracy for deep CNNs and (2) needing 16-bit floating-point or 8-bit fixed-point for a good accuracy. In this article, we propose a low-precision (8-bit) floating-point (LPFP) quantization method for FPGA-based acceleration to overcome the above limitations. Without any re-training, LPFP finds an optimal 8-bit data representation with negligible top-1/top-5 accuracy loss (within 0.5%/0.3% in our experiments, respectively, and significantly better than existing methods for deep CNNs). Furthermore, we implement one 8-bit LPFP multiplication by one 4-bit multiply-adder and one 3-bit adder, and therefore implement four 8-bit LPFP multiplications using one DSP48E1 of Xilinx Kintex-7 family or DSP48E2 of Xilinx Ultrascale/Ultrascale+ family, whereas one DSP can implement only two 8-bit fixed-point multiplications. Experiments on six typical CNNs for inference show that on average, we improve throughput by over existing FPGA accelerators. Particularly for VGG16 and YOLO, compared to six recent FPGA accelerators, we improve average throughput by 3.5 and 27.5 and average throughput per DSP by 4.1 and 5 , respectively.

On the design of radix-K approximate multiplier using 2D pseudo-booth encoding

In this paper, we propose energy-efficient unsigned approximate multipliers using the Pseudo-Booth (PB) encoding that are suitable for large dynamic-range operands thanks to leading zero remover (LZR) circuit. We have used our encoding form for both operands, so the proposed multiplier is called by two-dimensional Pseudo-Booth (2DPB) multiplier. The proposed multiplier accuracy can be adjusted by tuning the encoder radix and the truncation value. The efficiency of the proposed 2DPB multiplier has been evaluated by comparing its characteristics to those of six state-of-the-art approximate multipliers and the conventional (exact) multiplier in a TSMC-180 nm technology. The results reveal that the proposed 16-bit unsigned multiplier R8-T12, i.e., radix-8 and 12-bits truncation, provides up to 95% and 89% reductions in power-delay product (PDP) and power consumption, respectively, compared to the exact unsigned multiplier. It also provides up to 55% and 24.4% lower power-delay product (PDP), respectively, compared to the best of other approximate multipliers considered in this brief. Finally, the effectiveness of the proposed multiplier in real-life applications, including FIR filters and two image processing applications of smoothing and sharpening, is demonstrated.

Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications

Today, almost all computer systems use IEEE-754 floating point to represent real numbers. Recently, posit was proposed as an alternative to IEEE-754 floating point as it has better accuracy and a larger dynamic range. The configurable nature of posit, with varying number of regime and exponent bits, has acted as a deterrent to its adoption. To overcome this shortcoming, we propose <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fixed-posit</i> representation where the number of regime and exponent bits are fixed, and present the design of a fixed-posit multiplier. We evaluate the fixed-posit multiplier on error-resilient applications of AxBench and OpenBLAS benchmarks as well as neural networks. The proposed fixed-posit multiplier has 47%, 38.5%, 22% savings for power, area and delay respectively when compared to posit multipliers and up to 70%, 66%, 26% savings in power, area and delay respectively when compared to 32-bit IEEE-754 multiplier. These savings are accompanied with minimal output quality loss (1.2% average relative error) across OpenBLAS and AxBench workloads. Further, for neural networks like ResNet-18 on ImageNet we observe a negligible accuracy loss (0.12%) on using the fixed-posit multiplier.

An 8-bit Radix-4 Non-Volatile Parallel Multiplier

The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 μm2 with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 μW and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively.

Modeling of single/multiple-bit upset effects on logic circuits applying Recurrent Neural Network

This paper proposes a Recurrent Neural Network (RNN) method for modeling transient fault effects on microelectronic devices. RNNs can estimate the impacts of glitches propagated through the circuits, fast and accurately. The estimation phase begins with the learning of behavior of the gates, i.e., NOT, AND, NAND, etc. Then, it provides fast and meticulous evaluations of the transient fault influences on circuits. Simulation results illustrate that the RNN develops the capabilities of conventional methods to explicit forms and impacts of transient faults. The findings accrued from RNN analysis of a 32-bit multiplier, demonstrate 2736x time speed-up with the 4.13 of accuracy loss in contrast with the HSPICE’s simulation time and output values. Additionally, in terms of estimating multiple transient fault effects on the 4-bit Multiply and Accumulate (MAC) circuit, compare to HSPICE’s, there is 16.69x time-acceleration with the 0.048 penalties in output signals’ values. The model considers the triple masking effects, re-convergent fan-out, and fault influences during several clock cycles.

Demonstration of a 52-GHz Bit-Parallel Multiplier Using Low-Voltage Rapid Single-Flux-Quantum Logic

A high-throughput 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\times }$</tex-math></inline-formula> 4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the delays, and load dependency of the signal splitters. The key is to intentionally use both Josephson transmission lines and passive transmission lines for gate-to-gate wiring, even over short distances, to form the same structure wiring as the clock lines. The structure of the multiplier is based on a bit-parallel, gate-level pipeline to exploit throughput. The test chip was fabricated using the AIST 10-kA/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{^2}$</tex-math></inline-formula> , Nb/AlOx/Nb, 9-Nb-layer Advanced Process 2. The measured maximum operating frequency, throughput, and power consumption without cooling cost in the high-speed on-chip test were 52 GHz, 52 G-operations per second (GOPS), and 134 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\mu }$</tex-math></inline-formula> W, respectively. Although the switching speed of the Josephson junctions was reduced by 40 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\%}$</tex-math></inline-formula> owing to the low-voltage operation, the obtained clock frequency was as high as that demonstrated with the standard bias voltage. The energy efficiency was 381 tera-operations per second per watt (TOPS/W) at 4.2 K. Further improvement in energy efficiency is expected by using low-voltage half-flux-quantum (LV-HFQ) circuits and shrinking the size of Josephson junctions.

Modified Binary Vedic Multiplication Using Carry Save Adder

This paper presents modified binary Vedic multiplication using carry save adder. The suggested modified binary Vedic multiplication technique is more efficient in terms of delay. The proposed circuit is implemented in Verilog HDL. The Xilinx ISE Design Suite 14.6 is used for circuit synthesis. The simulation done for 4-bit ,8-bit 16-bit multiplication operations. In this paper, the simulation waveforms are shown only for 4-bit and 8-bit multiplication operation based on the modified Vedic multiplication technique using carry save adder. The vedic multiplication method can be extended for a larger bit size. The delay compared with normal multiplication technique.

A Low-Complexity Edward-Curve Point Multiplication Architecture

The Binary Edwards Curves (BEC) are becoming more and more important, as compared to other forms of elliptic curves, thanks to their faster operations and resistance against side channel attacks. This work provides a low-complexity architecture for point multiplication computations using BEC over GF(2233). There are three major contributions in this article. The first contribution is the reduction of instruction-level complexity for unified point addition and point doubling laws by eliminating multiple operations in a single instruction format. The second contribution is the optimization of hardware resources by minimizing the number of required storage elements. Finally, the third contribution is to reduce the number of required clock cycles by incorporating a 32-bit finite field digit-parallel multiplier in the datapath. As a result, the achieved throughput over area ratio over GF(2233) on Virtex-4, Virtex-5, Virtex-6 and Virtex-7 Xilinx FPGA (Field Programmable Gate Array) devices are 2.29, 19.49, 21.5 and 20.82, respectively. Furthermore, on the Virtex-7 device, the required computation time for one point multiplication operation is 18 µs, while the power consumption is 266 mW. This reveals that the proposed architecture is best suited for those applications where the optimization of both area and throughput parameters are required at the same time.

High accurate multipliers using new set of approximate compressors

Approximate multipliers play vital role in the error-resilience applications by balancing accuracy and power efficiency. In this article, we improved the accuracy of approximate multipliers using a set of proposed approximate compressors which are able to compress any number of inputs to arbitrary numbers of output bits. To achieve better accuracy, probability of being one in the input bits is used to determine the compression ratio. Also, a novel scheme for allocating approximate and exact compressors in PPM is proposed to decrease column reduction stages. Error metrics namely PE, MED, MRED, and NED are calculated to evaluate accuracy of our approximate compressors. Experimental results show an average of 35% accuracy improvement, in comparison with the previous approximate compressors. We implemented four different multipliers including 8-bit, 12-bit, 16-bit, and 24-bit multipliers to prove goodness of our proposed algorithm. The multipliers are designed by Verilog and synthesized in a 45-nm standard CMOS technology. The experimental results demonstrate major accuracy superiority of our proposed multipliers in comparison with the state of the art approximate multipliers in terms of MED, MRED, and NED. According to the experimental results, the delay is improved 22%, on average, compared with exact multipliers.

Machine-Learning-Based Self-Tunable Design of Approximate Computing

Approximate computing (AC) is an emerging computing paradigm suitable for intrinsic error-tolerant applications to reduce energy consumption and execution time. Different approximate techniques and designs, at both hardware and software levels, have been proposed and demonstrated the effectiveness of relaxing the average output quality constraint. However, the output quality of AC is highly input-dependent, i.e., for some input data, the output errors may reach unacceptable levels. Therefore, there is a dire need for an input-dependent tunable approximate design. With this motivation, in this article, we propose a lightweight and efficient machine-learning-based approach to build an input-aware design selector, i.e., quality controller, to adapt the approximate design in order to meet the target output quality (TOQ). For illustration purposes, we use a library of 8-bit and 16-bit energy-efficient approximate array multipliers with 20 different settings, which are commonly used in image and audio processing applications. The simulation results, based on two sets of images, including an 8 Scene Categories Dataset, which is a benchmark of images data set, demonstrate the effectiveness of the lightweight selector where the proposed tunable design achieves a significant reduction in quality loss with relatively low overhead.

Image encryption method based on improved ECC and modified AES algorithm

Currently, embedded systems can be found everywhere in quotidian life. In the development of embedded systems, information security is one of the important factors. Encryption is an efficient technique to protect information against attacks. However, because of constraints, existing encryption functions are not compatible and do not agree with real-time applications in embedded systems. In this paper, an improved cryptographic approach with a high level of security and high speed is put forward. Our work uses an efficient version of a hybrid scheme comprising an Advanced Encryption Standard (AES) - Elliptic Curve Cryptography (ECC) for medical image encryption, which combines the benefits of the symmetric AES to speed-up data encryption and asymmetric ECC in order to secure the interchange of a symmetric session key. The contribution of this paper consists of the following two main points: First, we put forward an optimized ECC hardware architecture to respect the compromise between area, power dissipation, and speed. Thus, we primarily utilize only two multipliers to develop the Point Addition (PA) block and the Point Doubling (PD) block, which reduces time complexity. Then, a 32-bit multiplier and a 32-bit inverter architecture based on shifts and XORs are proposed to reduce power consumption and area occupancy. Second, for image encryption, we primarily propose to modify the AES by eliminating the mix-columns transformation and replacing it with a permutation based on the shifts of columns, which decreases time complexity while maintaining the Shannon diffusion and the confusion principle. Then, an adjustment of the rearrangement of the general structure is given to enhance the entropy value. The global cryptosystem is implemented using a co-design approach where the modified AES runs on the NIOS II processor, and the scalar ECC multiplication is designed as a hardware accelerator. The suggested cryptographic system spends much less execution time, which is a significant factor for being applied in practice. Security analysis is successfully performed, and our experiments prove that our proposed technique provides the basics of cryptography with more simplicity and correctness. In fact, the results of the evaluation prove the effectiveness, rapidity and high security of the suggested algorithm.

CMOS Implementation of a Novel High Speed 4:2 Compressor for Fast Arithmetic Circuits

This paper deals with the design and analysis of a new 4-2 compressor which can be used in high-speed multipliers. The proposed compressor features eliminated glitch at the output waveform. By optimum tuning of the width of the transistors, C out is produced more quickly, and therefore higher operating speeds can be achieved. The effect of process variation on the circuit has been studied and a new structure is proposed to overcome the effect of process variation by utilizing a reference voltage generator circuit. A 32 × 32-bit multiplier has been developed utilizing these compressors in order to evaluate the new compressor in a practical environment. The total multiplier circuit was simulated with HSPICE simulator (BSIM3v3 parameters) using CMOS standard cell library of 0.18 µm and the Layouts were extracted with Cadence Virtuoso v 5.1 Layout Plus tool. The simulation results represent 185 × 10−3 pj Power-Delay-Product (PDP) and 40 pj × ps Energy Delay Product (EDP) with 221 ps delay from input to output.

Redundant Crossfire: A Technique to Achieve Super-Resolution in Neurostimulator Design by Exploiting Transistor Mismatch

A high-resolution neurostimulator is the essential component of many bidirectional neural interfaces. In practice, the effective resolution of fully integrated neurostimulator designs is often hindered by the transistor mismatch, especially in submicrometer CMOS processes. In this article, we present a new circuit technique called redundant crossfire (RXF) to address this challenge. It is derived from our redundant sensing (RS) framework, which aims at engineering information redundancy into the system architecture to enhance its effective resolution. RXF involves combining (i.e., crossfiring) the outputs of two or more current drivers to form a redundant structure that, when properly configured, can produce accurate current pulses with an effective super-resolution beyond the limitation commonly permitted by the physical constraints. Unlike any previous works, the proposed technique achieves high-accuracy by directly exploiting the random transistor mismatch with an excessively large mismatch ratio of 10%–20%. The effectiveness of RXF is verified through both Monte Carlo simulations and measurement results of a fully integrated neurostimulator chip. Equipped with a 5-bit current digital-to-analog converter (IDAC) and two 4-bit current multipliers, the stimulator achieves an effective resolution of 9.75 bits in a 1.1-mA full range. An application of the fabricated chip is to deliver neuro-feedback to a human amputee through peripheral nerves where the amplitude of stimulation pulses is accurately controlled to encode the tactile response’s intensity.