16-bit Multiplier Research Articles

Delay and area efficient approximate multiplier using reverse carry propagate full adder

The performance and power of error resilient applications will rise with a decrease in designing complexness due to approximate computing. This paper includes the new method for the approximation of multipliers. Variable likelihood terms are produced by the alteration of partial products of the multiplier. Based on the probability statistics, the accumulation of altered partial products leads to the variation of logic complexity. Here the estimate is implemented in 2 variables of 16-bit multiplier and in the final stage with reverse carry propagate adder(RCPA). The reverse carry propagate adder have carry signal propagation from the most significant bit(MSB) to the least significant bit(LSB), which results in greater relevance to the input carry than the output carry. The technique of carry circulation in reverse order with delay variations increases the stability. Utilizing the RCPA in approximate multiplier provide 21% and 7% improvements in area and delay. On comparing, this structure is resilient to delay variations than the ideal approximate adder.

Inverted Gate Vedic Multiplier in 90nm CMOS Technology

This paper proposes the design and implementation of an enhanced binary multiplication technique. Vedic Mathematics is a system of mathematics that was discovered by Indian mathematician Jagadguru Shri Bharathi Krishna Tirthalji in the period between 1911 and 1918. The main objective of this paper is to design an improved binary multiplier which is faster and low-powered. The performance of our proposed full adder design is proven to be more effective in comparison with the standard full adder cell both designed in 90nm. The proposed modified 2-Bit and 4-Bit Vedic multipliers also beat the existing Vedic multiplier based in Urdhva Tiryagbhyam sutra in terms of operating frequency, energy and area. ThedesignsareimplementedoncadenceVirtuoso90nmCMOStechnology operating at 2V supply. Comparedtotheexisting standard fulladderdesigns in 90nm, the proposed implementation has shown that it offers significant improvements in terms of power and speed consuming 60% less power and is able to operate 20% faster. The proposed 2-Bit multiplier operated at 2V is proven to be more effective. The design was further extended to realise a 4-Bit multiplier. The power consumed by the standard 4- Bit multiplier designed using standard 90nm cells was 361.2µW and the power consumed by the proposed 4-Bit multiplier design was found to be 290.2µW, which reflectsa 20% decrease in the power usage.

FPGA-Based Multi-Level Approximate Multipliers for High-Performance Error-Resilient Applications

This paper presents approximate multipliers which are efficiently deployed on Field Programmable Gate Arrays (FPGAs) by using newly proposed approximate logic compressors at different levels of accuracy. Our approximate multiplier designs offer higher gains of power-delay-area products (PDAP) than those of the state-of-the-art works at comparable accuracies. Furthermore, in terms of delay, occupied area, and dynamic power dissipation, our designs are much better than Lookup Table based multiplier Intellectual Properties that are available on an FPGA. Particularly, our proposed 8-, 16-, and 32-bit multipliers can deliver PDAP gains up to 7.1 x, 8.3 x, and 5.0 x, respectively. The effectiveness and applicability of our designs are also demonstrated by image processing applications such as image multiplication and sharpening. The experiments show that for the image sharpening, our 8 x 8 multipliers can deliver a good peak signal-to-noise ratio (PSNR) of 46.81 dB, a structural similarity index metric (SSIM) of 0.9989, and a dynamic power saving of up to 36.7% with regard to the exact multiplier. For the image multiplication, approximate 16 x 16 multipliers can offer a high PSNR of 80.25 dB, an SSIM of 1.0, and a dynamic power saving of up to 58.15%. From these demonstrations, the proposed multipliers are expected to be appropriate with high-performance and low-power error-resilient applications.

A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism

The radix-4 Booth algorithm is widely used to improve the performance of multiplier because it can reduce the number of partial products by half. However, numerous additional encoders and decoders would cause the power consumption of the Booth multiplier to be considerable. In this paper, a new radix-4 Booth pre-encoded mechanism is proposed to reduce the power consumption of the Booth multiplier. The proposed design can effectively reduce the power of the Booth multiplier dissipated in the redundant activities by disabling the Booth encoders and decoders from unnecessary working. Particularly, since the control signals are generated early at the pipeline input register before the multiplier, the performance of our design is better than the traditional Booth multiplier. Based on the TSMC 40 nm technology, the simulation results show that the proposed pre-encoded mechanism can reduce the dynamic and static power by 45% and 65%, respectively, compared to the traditional 16-bit radix-4 Booth multiplier. Compared to the previous designs, the proposed design keeps the feature of race-free and has lower power consumption. Even compared to the approximate design, the proposed design has better power efficiency and can provide the exact products.

Implementation of Low Power and Area Efficient Vedic Multiplier

Designing a low power consuming and area efficient Vedic Multiplier using Hybrid Full Adder. In this paper, Conventional CMOS (CCMOS) Full Adders involved in a conventional Vedic multiplier is replaced with Hybrid Full adders to achieve reduction in power consumption and area. In the proposed system ripple carry adders involved in Vedic multiplier are designed using Hybrid Full Adder. The design is done for 2-bit and it is extrapolated to 16-bit. Performance parameters such as power consumed and area between Vedic multiplier involving CCMOS and Hybrid Full Adder is done and a comparative study over them is made. Significant improvement is achieved in this implementation and the layout design is also implemented for the 2-bit, 4-bit, 8-bit and 16-bit Vedic multiplier for both Conventional CMOS and Hybrid Full-Adder logic styles. The implementation is carried out using Tanner EDA tool under 250-nm technology.

Modelling and Simulation of a Reversible Quantum Logic based 4 × 4 Multiplier Design for Nanotechnology Applications

Reversible logic has become one of the most suitable techniques in low power design because of its zero power dissipation property. Extensive research is underway to construct efficient reversible logic gates and reversible circuits such as adders, multipliers and dividers because of its wide applications in optical information processing, nanotechnology, DNA computing and quantum computation fields. In this paper, first a 4 × 4 reversible gate TKG is presented which has low quantum cost followed by the design of a 4-bit reversible multiplier. This multiplier design utilizes the proposed TKG to generate partial products and duplication of original bits, which not only eliminates the need of fan-out generation circuit but also reduces the delay of the circuit. Extensive comparisons of the proposed gate and multiplier are drawn with existing counter parts in the literature and it is envisaged that the proposed designs are efficient and also there is a significant improvement and reduction in the quantum cost of the circuit along with the delay due to the use of TKG Gate.

A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing

This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM) that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic to accommodate a wide range of bit-widths, from single to 32 or 64 bits, as well as a complete set of operation types, including integer and floating-point addition, multiplication, and division. This approach provides the flexibility and programmability necessary for evolving software algorithms ranging from neural networks to graph and signal processing. The proposed design was implemented in a small Internet of Things (IoT) processor in the 28-nm CMOS consisting of a Cortex-M0 CPU and 8 CRAM banks of 16 kB each (128 kB total). The system achieves 475-MHz operation at 1.1 V and, with all CRAMs active, produces 30 GOPS or 1.4 GFLOPS on 32-bit operands. It achieves an energy efficiency of 0.56 TOPS/W for 8-bit multiplication and 5.27 TOPS/W for 8-bit addition at 0.6 V and 114 MHz.

Design and Implementation of Compressor based 32-bit Multipliers for MAC Architecture

Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.

Implementation of multi-precision floating point divider for high speed signal processing applications

The introduction of fused multiplier and add technique enhances design metrics of floating point (FP) arithmetic operations. Particularly Newton–Raphson (NR) based division algorithm is popular choice to SRT division algorithms. This paper proposes 32-bit FP division using NR computational division technique with pipelining method capable of doing high speed signal processing operations. The proposed divider used as IP core and make it as optimal choice to speed up FP operations. It improves rounding accuracy in addition with reduction in area overhead. The NR computational calculations are implemented by iteratively using 32-bit FP multiplier and adder. The key module used for calculating significand (mantissa) part is 24-bit Wallace tree multiplier using carry save adders. The Wallace multiplier provides higher computational speed, hence, is effectively utilized as a part of FP divider. The proposed pipelined FP divider is fully combinational circuit with clock and data gating applied to reduce the dynamic power consumption, delay and area overhead designed for signal processing applications. It also improves the accuracy of the result. The operands are represented and operated using IEEE 754 standard. The operation and results are validated through simulation using VIVADO software and implemented on Xilinx-7 series, ARTIX field programmable gate array.

Effective Designs of Reversible Vedic Multiplier

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

Implementation of energy-efficient approximate multiplier with guaranteed worst case relative error

Existing design methods for approximate multipliers typically rely on exhaustive simulation to determine the approximation error. However, this approach is not tractable for complex designs. In this paper, a two-dimensional piecewise linear approximation method for multiplication that formally guarantees the maximum error is proposed. Based on this method, a design procedure to implement energy-efficient approximate multipliers is also proposed. Three 32-bit unsigned approximate multipliers with guaranteed maximum errors of 12.5%, 3.13% and 0.78% were realized using the design procedure. The efficiencies of the proposed designs were evaluated by comparing their parameters with that of the exact and state-of-the-art approximate multipliers. The proposed designs deliver up to 91.8% (62.1%) energy saving when compared with that of exact (approximate) multipliers. The effectiveness of the approximate multipliers was also assessed in an image smoothening application.

Hardware Implementation of FFT/IFFT Algorithms Incorporating Efficient Computational Elements

Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) computations involve quite a large number of complex multiplications and complex additions. Optimizing the FFT processing elements in terms of complex multiplication reduces area and power consumption. In this paper, complex multipliers in the FFT processors are replaced by area and power efficient approximate multipliers. Approximate arithmetic computation appears to be effective solution for the systems that exhibit an intrinsic error tolerance. The computational errors arising because of approximation can be considered as trade-off for the significant gains in power and area. Approximate 8- and 16-bit multipliers are used in radix-2 butterfly unit which is the crucial computational component in FFT/IFFT processing. The designed FFT/IFFT processing units are analyzed, synthesized and simulated in Altera Cyclone II EP2C35F672C6 Field Programmable Gate Array (FPGA) device. Experimental results show that the proposed 16-point FFT architecture incorporating approximate complex multiplier achieves an area and power efficiency of 33.47% and 1.8% respectively compared to accurate 16-point FFT processor. The 8-point and 16-point Decimation In Time (DIT)—FFT incorporating approximate computational elements operate at a speed of 26.69 Gbps and 46.20 Gbps, respectively.

A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications

Nonvolatile logic implemented by memristor devices is a potential candidate for inherent logic-in-memory architecture. Majority-inverter graph (MIG) logic is a novel logic-structure compared with conventional AND/OR/INV graphs logic. In this brief, MIG logic constructed by memristors is proposed to implement the stateful logic arithmetic. A design of full adders based on MIG logic is proposed, followed by a 4-bit Wallace tree multiplier based on the MIG logic to implement in-situ store. A test chip controlled by a FPGA is designed to verify its feasibility. Compared with multipliers implemented by conventional logic, this method has fewer steps and smaller area, making it suitable for frequent-off and instant-on circuits in IoT applications. The experimental results have proved its significance on the grounds that the 4-bit multiplier only needs 18 processing steps with 51 memristor cells to complete a multiplication arithmetic whereas, by contrast, one conventional 4-bit binary multiplier requires 648 MOSFETs and 124 steps while IMP based 4-bit multiplier logic requires 112 CRS units and 221 steps to operate a multiplying computation.

Area and Energy-Efficient 4-2 Compressor Design for Tree Multiplier Implementation

Redundant gates of 4-2 compressor (hereafter, it is referred as 42C) has been removed by simplification of compressor output Boolean expression, that results in power consumption minimization. Further, the proposed design is implemented in full swing gate diffusion input logic, a low-power design technique with minimum transistor count. To evaluate the performance of existing and proposed compressor designs, they are simulated using SPICE simulation at 45 nm technology model. Also, the area is calculated from their corresponding generated layouts for the same technology model. From the simulation results, it is observed that the proposed compressor has shown performance improvement in terms of power delay product by 45% than the recently reported compressor. Further, to study the performance of proposed compressor in an application environment, a 16-bit multiplier is implemented. Its simulation results confirmed that the performance improvement is consistent in the multiplier too.

Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder

Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier “bypass zero feed multiplicand directly,” based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35% predominantly for a 32-bit multiplier.

A comprehensive compact model for the design of all-spin-logic based circuits

By relying on pure spin transmission, low-frequency charge-spin conversion, and neuron-like mechanism, All Spin Logic (ASL) has the potential to outperform CMOS technology in logic design and especially in neuromorphic computing, with improved fabrication process and material technology in the future. As ASL technology is gaining in maturity, compact models are needed to fill the gap between application requirements and circuit fabrication. However, defining such a model is a tedious task due to the numerous physical parameters to consider and the need for flexibility to explore design tradeoffs. In this paper, we propose an accurate, generic, scalable, and easy-to-use compact model for ASL devices. The model has been validated by comparing with experimental results, which allows investigating the impact of device characteristics such as channel length and channel width on the propagation delay. The model has been implemented in Cadence using in Verilog-A, which allows running transient simulations and comparing the implementations of 4-bit adder and multiplier circuits regarding the area, energy and delay metrics.

Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error

Approximate computing exploits the fact that many applications are inherently error resilient. In order to reduce power consumption, approximate circuits such as multipliers have been employed in these applications. However, most current approximate multipliers are based on $ad~hoc$ circuit structures and, for automated circuit approximation methods, large efficient designs are difficult to find due to the increased search space. Moreover, existing design methods do not typically provide sufficient formal guarantees in terms of error if large approximate multipliers are constructed. To address these challenges, this brief introduces a general and efficient method for constructing large high-quality approximate multipliers with respect to the objectives formulated in terms of the power-delay product and a provable error bound. This is demonstrated by means of a comparative evaluation of approximate 16-bit multipliers constructed by the proposed method and other methods in the literature.

An asynchronous mesh NoC based booth multiplication

The multiplier is one of the most important arithmetic units, which is an essential part of an IC system and affects its efficiency dramatically. The Booth structure of a multiplier is a wide-used and efficient structure of real IC systems, and the performance of a Booth multiplier would be mainly determined by partial product issues, e.g., multiplication and addition, as well as the frequency of the clock. Then, one of the potential improvements would be the asynchronous control to reduce power by cancelling the global clock, the other be the structure and implementation of the algorithm for high performance, and the last could be the benefits of reconfiguration for sharing process elements. In this paper, we proposed a Booth algorithm which organized by an asynchronous NoC, e.g., the partial product generators are located into a configurable network, and other part of the circuit are organized and adjusted by an asynchronous mechanism. The design is finally implemented by an 8-bit asynchronous Booth multiplier, which is synthesized and post simulated with a Xilinx Virtex-7 FPGA development board.

High Performance Modified Static Segment Approximate Multiplier based on Significance Probability

Achieving high accuracy has become a key design objective in high quantity digital data computing devices. To enhance the accuracy, a high performance Modified Static Segment approximate Multiplier (MSSM) is proposed in this paper. It increases the accuracy based on the negating lower order significant information of input operands using Significance Estimator Logic Circuit (SELC). The performance of proposed MSSM is compared with the existing approximate multipliers such as a Dynamic Segment approximate Multiplier (DSM) and Static Segment approximate Multiplier (SSM) for all input combinations. These multipliers are implemented and simulated using Xilinx 14.2 ISE. In MSSM method, 99% of average computational accuracy can be achieved for a 16-bit multiplication even with an 8 × 8-bit multiplier from all combinations of input operands instead of 95% of average computational accuracy from 61% of input operand pair in the existing SSM method. The proposed 16-bit MSSM offers a savings of 83.45% LUTs, 38.78% power and it exhibits 24.40% less delay, 0.6% less computational accuracy than the existing DSM.

Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique

Vedic mathematics is an old mathematics which is more effective than other mathematic procedures. Vedic maths is utilized as a part of numerous applications, for example, hypothesis of numbers, compound duplications, squaring, cubing, square root and solid shape root and so on. Absolutely there are 16 sutras and 14 sub-sutras in Vedic maths. Among those sutras, just 3 sutras and 2 sub-sutras are utilized for augmentation. Multiplier is a very important part of a microprocessor as multiplication is performed continuously in all calculative procedures. This paper is in importance of a 8-bit multiplier designed in 90 nm technology. Urdhva-Tiryakbyham is the sutra that is used for multiplication in Vedic mathematics. Actualizing the different scientific operations utilizing Vedic Mathematics causes us accomplish better speed, bring down unpredictability and higher execution.[2] The technique used is Gate Diffusion Input (GDI) which is a more refined way to design a circuit which less complex than circuits designed by other techniques.