Abstract
This paper proposes the design and implementation of an enhanced binary multiplication technique. Vedic Mathematics is a system of mathematics that was discovered by Indian mathematician Jagadguru Shri Bharathi Krishna Tirthalji in the period between 1911 and 1918. The main objective of this paper is to design an improved binary multiplier which is faster and low-powered. The performance of our proposed full adder design is proven to be more effective in comparison with the standard full adder cell both designed in 90nm. The proposed modified 2-Bit and 4-Bit Vedic multipliers also beat the existing Vedic multiplier based in Urdhva Tiryagbhyam sutra in terms of operating frequency, energy and area. ThedesignsareimplementedoncadenceVirtuoso90nmCMOStechnology operating at 2V supply. Comparedtotheexisting standard fulladderdesigns in 90nm, the proposed implementation has shown that it offers significant improvements in terms of power and speed consuming 60% less power and is able to operate 20% faster. The proposed 2-Bit multiplier operated at 2V is proven to be more effective. The design was further extended to realise a 4-Bit multiplier. The power consumed by the standard 4- Bit multiplier designed using standard 90nm cells was 361.2µW and the power consumed by the proposed 4-Bit multiplier design was found to be 290.2µW, which reflectsa 20% decrease in the power usage.
Highlights
With the advent of VLSI technology and the exponential growth in the number of transistors on the chip, there is a need for newer architectures to be faster, and at the same time, power consumption to be at its minimum
This paper presents a way of modifying the existing design of the Vedic multiplier to suit for various applications
Various multipliers and dividers based on Vedic sutras addressed in [6] and the authors conclude that the use of these sutras in the computing algorithm of the digital system would reduce the complexity of design, area, execution time and power consumption
Summary
This paper presents a way of modifying the existing design of the Vedic multiplier to suit for various applications. The modified Full adder and 2-Bit Vedic multiplier are proved to be much more efficient when compared to their conventional standard designs. The proposed design of the 4-Bit multi- plier using these modified designs helps improve the overall performance of the system. Vedic multiplications techniques are proven to be more effective than conventional methods [13], which is the main driving factor for our study into Vedic mathematics. Various multipliers and dividers based on Vedic sutras addressed in [6] and the authors conclude that the use of these sutras in the computing algorithm of the digital system would reduce the complexity of design, area, execution time and power consumption. Complexity of the circuits can be reduced by using techniques like Gate Diffusion In- put (GDI) as studied in [11]
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