Abstract
Every digital circuits need processors. Every processor performs arithmetic and logical operations. There are four arithmetic operations out of which multiplication is one of the main operation. To perform multiplication, multipliers are used. Various algorithms are used to implement multipliers. Vedic algorithm is one of the algorithm and is designed using ancient Vedic sutras. In this paper design and implementation of 4-bit vedic multiplier is done and the results are compared with 4-bit array multiplier. From the result it is observed that 4-bit vedic multiplier is efficient in terms of speed. There are 16 sutras out of these URDHVA TRIYAGBHYAM sutra is used to decrease the delay of the multiplier. This is designed using Cadence tool 45 nm technology.
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