Design and implementation of 8-bit vedic multiplier using mGDI technique

Abstract

The main constraints in recent trends of VLSI technology are power, area and delay. CMOS designs occupy more area and dissipate more power. Power dissipation results in heating up of an IC which directly affects the reliability and performance. Multipliers are the integral part of major application systems like Microprocessor, Digital Signal Processor (DSP) etc., so it is necessary to optimize the multiplier unit to build an efficient processor. In this paper, 8-bit Vedic multiplier is proposed using modified Gate Diffusion Input (mGDI). 8-bit Vedic multiplier is designed using Urdhva Tiryagbhyam sutra with 4 numbers of 4-bit Vedic multiplier and 3 adder circuits. The proposed mGDI based multiplier consumes 66% less area, 76.1% less power and 60% less delay when compared to conventional CMOS design. The proposed multiplier is implemented in cadence virtuoso tool on 180nm technology.