Design and Implementation of 8-Bit Vedic Multiplier in 18nm FinFET Technology

Abstract

In a digital signal processor, a multiplier is a crucial hardware component. Therefore, a fast and efficient multiplier plays a critical role in designing any digital processor. This project aims to design a fast, low-power, area-optimized Vedic multiplier. The Vedic multiplier uses a technique called “Urdhva Tiryagbhyam” sutra, which translates to “Vertically and crosswise”. It is one of the fastest techniques to perform multiplication. The design 8-Bit Vedic multiplier is carried out using the 18nm FinFET technology. The multiplier designed has an operating frequency ranging from 2GHz to 4GHz with the operating voltage ranging from 0.8V to 1V. The transient simulations run on the design verifies the functionality of the designed multiplier. The Layout Versus Schematic (LVS) software tool verifies that the layout designed corresponds to the designed schematic. The Design Rule Check (DRC) tool ensures the layout meets all the foundry constraints. Upon applying all the constraints on the operation, the power dissipated by the presented 8-bit Vedic multiplier is 782.4nmW and gives rise to a propagation delay of 1.677ns when the simulation is performed at an operating voltage of 0.8V at 4GHz frequency.