6T SRAM Research Articles

MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator

Lattice-based cryptography (LBC), exploiting learning with error (LWE) problems, is a promising candidate for postquantum cryptography. The number theoretic transform (NTT) is the latency- and energy-dominant process in the computation of LWE problems. This article presents a compact and efficient in-MEmory NTT accelerator, named MeNTT, which explores an optimized computation in and near a 6T SRAM array. Specifically designed peripherals enable fast and efficient modular operations. Moreover, a novel mapping strategy reduces the data flow between the NTT stages into a unique pattern, which greatly simplifies the routing among processing units (i.e., the SRAM column in this work), reducing the energy and area overheads. The accelerator achieves significant latency and energy reductions over prior arts.

A Single-Bitline 9T SRAM for Low-Power Near-Threshold Operation in FinFET Technology

A Single-Bitline 9T SRAM for Low-Power Near-Threshold Operation in FinFET Technology

A highly reliable radiation tolerant 13T SRAM cell for deep space applications

This paper proposes a highly reliable radiation-tolerant 13T (HRRT 13T) SRAM cell for deep-space applications. The proposed SRAM cell design can effectively tolerate radiation events. The design metrics of the proposed SRAM cell are compared with conventionally used SRAM cells like QUCCE 10T, QUCCE 12T and standard 6T SRAM cells. The proposed SRAM cell consumes 9.4% and 14% lesser hold power (HPWR) compared to QUCCE 10T and QUCCE 12T SRAM cells, respectively. The proposed SRAM cell exhibits 12.7%, 3.63% and 11.7% shorter read access time (TRA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at a nominal supply voltage (VDD) of 0.7 V. The proposed HRRT 13T SRAM cell exhibits higher read stability compared to other conventionally used SRAM cells. This has been validated by 2.92×, 2.33× and 2.06× higher read static noise margin (RSNM) exhibited by the proposed cell compared to the 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed SRAM cell exhibits high radiation tolerance capability compared to the conventionally used SRAM cells. This has been proved by 94.1%, 17.8% and 10.0% higher critical charge (QC) of the proposed cell compared to 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed cell achieves all these improvements at the expense of 1.05×, 1.38× and 1.36× longer write delay (TWA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at VDD = 0.7 V. Extensive simulations on SPICE using 16-nm CMOS technology are performed to validate the theoretical design of the proposed SRAM cell.

A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications

This paper proposes a symmetric eight transistor-three-memristor (8T3R) non-volatile static random-access memory (NVSRAM) cell. Non-volatile operation is achieved through the use of a memristor element, which stores data in the form of its resistive state and is referred to as RRAM. This cell is able to store the information after power-off mode and provides fast power-on/power-off speeds. The proposed symmetric 8T3R NVSRAM cell performs better instant-on operation compared to existing NVSRAMs at different technology nodes. The simulation results show that resistance of RAM-based 8T3R SRAM cell consumes less power in standby mode and has excellent switching performance during power on/off speed. It also has better read and write stability and significantly improves noise tolerance than the conventional asymmetrical 6T SRAM and other NVSRAM cells. The power dissipation is evaluated at different technology nodes. Hence, our proposed symmetric 8T3R NVSRAM cell is suitable to use at low power and embedded applications.

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell.

Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications

With the advancement of technology, the size of transistors and the distance between them are reducing rapidly. Therefore, the critical charge of sensitive nodes is reducing, making SRAM cells, used for aerospace applications, more vulnerable to soft-error. If a radiation particle strikes a sensitive node of the standard 6T SRAM cell, the stored data in the cell are flipped, causing a single-event upset (SEU). Therefore, in this paper, a Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T (SARP12T) SRAM cell is proposed to mitigate SEUs. To analyze the relative performance of SARP12T, it is compared with other recently published soft-error-aware SRAM cells, QUCCE12T, QUATRO12T, RHD12T, RHPD12T and RSP14T. All the sensitive nodes of SARP12T can regain their data even if the node values are flipped due to a radiation strike. Furthermore, SARP12T can recover from the effect of single-event multi-node upsets (SEMNUs) induced at its storage node-pair. Along with these advantages, the proposed cell exhibits the highest read stability, as the ‘0’-storing storage node, which is directly accessed by the bitline during read operation, can recover from any upset. Furthermore, SARP12T consumes the least hold power. SARP12T also exhibits higher write ability and shorter write delay than most of the comparison cells. All these improvements in the proposed cell are obtained by exhibiting only a slightly longer read delay and consuming slightly higher read and write energy.

A SMART DESIGN OF A MULTI-DIMENSIONAL ANTENNA TO ENHANCE THE MAXIMUM SIGNAL CLUTCH TO THE ALLOWABLE STANDARDS IN 5G COMMUNICATION NETWORKS

At the current deep submicron and nanometer level, the leakage power is becoming the major contributor to overall power consumption in modern VLSI circuits. This research paper presents a novel approach to reducing leakage power by inserting two leakage transistors in the middle of pull-down and pull-up paths. Out of these two leakage transistors, one is the PMOS transistor, and another one is the NMOS transistor. This research work presents a dynamic CMOS inverter and 6T SRAM cell with and without transmission gate (TG) to reduce leakage power using the LECTOR and LECTOR-B techniques. The Cadence Virtuoso simulation tool is used to presents the results in terms of static power. Using the 45-nm technology node, the performance in terms of static power is analyzed. It is observed that using LECTOR and LECTOR-B techniques, the overall reduction in static power is 26% and 20%, respectively, compared to the conventional design for SRAM cell. Similar improvements are also noted for dynamic CMOS inverter and TG SRAM cell. Since the operating range of 5G communication networks is the same as that of the previous generation, there are no difficulties in using these antennas on 5G communication networks. For any technology, the use of antennas makes it possible to bring data rates closer to maximum values. The new technology that uses separate receivers and transmitters on the same frequency band has further increased the speed of receiving and transmitting data. The design of the existing 4G modem provides for the use of antenna technology. The proposed model provides the construction of a multidimensional antenna. The other passive devices it has a one-way direction, which increases the received signal and reduces the amount of interference from the sides to the back. Therefore, the proposed model possible to increase the signal level to acceptable values, even at unstable reception levels thereby increasing the speed of receiving and transmitting the information. The undoubted advantage of panel antennas is their low cost and exceptional reliability. There is practically nothing in the design that can be broken even when falling from a great height. The only weak point is the high-frequency cable, which can break at the point where it enters the case. To extend the life of the device, the cable must be securely connected.

Enhancing Energy Efficiency of Sram through Optimization of Sram Array Structures

Reliability is a major concern in the microprocessor industry. In terms of power consumption, SRAM plays a key role in improving processing performance. Improving SRAM efficiency requires changes to the array structure. A general method in which the SRAM array has more rows than columns.The above techniques are proposed to improve efficiency by 10% for 8kbit and 40% for 64kbit at the same SRAM byte density and supply voltage. Implement suggested deep submicron technology for better reliability. Many proposed designs focus on low power consumption, often with reduced response times.As the technology scales, the power consumption of on-chain system devices with gate leakage, subthreshold current, and tunneling increases significantly. Small SRAM capabilities are important.This task demonstrates the potential of using larger SRAM array structures to achieve better SRAM energy efficiency, especially when the number of rows is less than the number of low-power columns. Compared to traditional 8T SRAM, the proposed 10T cell uses less power, has a different temperature and better performance.

Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM

This paper explores an ultra-low-power 10T subthreshold SRAM with high stabilities based on 10-nm FinFETs. To prove the superiority of the proposed 10T SRAM's performance, a comparison has been done with existing SRAMs such as the 6T, ST2, DIRP10T, PPN10T, and FC11T at VDD = 0.3 V. The proposed cell offers 2.08X/1.31X/1.03X higher read-stability compared to 6T/ST2/PPN10T due to the use of the read decoupling technique. Writability is increased at least 1.28X by temporarily floating the data node. In the proposed single-ended design, read-bitline does not need to be precharged to VDD to execute read operation, therefore, improving dynamic read power by at least 2.69X. Because of its single-ended nature, the suggested 10T SRAM's dynamic write power consumption is lowered by at least 1.86X. The stacked structure used in the cell core and bitline leakage removed in the read path minimize leakage power by at least 1.50X. Therefore, the proposed design can be an appropriate choice for ultra-low-power applications.

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

In this paper, a single-ended, dual port, 1R1 W seven transistor-based static random access memory bit cell is presented. The cell is designed based on a detailed review of various pre-existing 7T cells. All the cells in the paper are evaluated at 32 nm technology and supply voltage of 0.8 V. The static analysis reveals that the hold/read noise margins for the proposed cell are 324 mV each, whereas the write margin is 488 mV. Successful read and write operation for the cell requires a pulse-width of 5 ps and 0.14 ns, respectively. The temperature variation and process corner analysis are used to justify the reliability for the proposed cell. The former analysis yields 0.15 and 0.24 mV/°C variation in the HSNM/RSNM, and WM for the cell. The current ratio for the cell is comparatively higher than other cells. The leakage power consumption for the cell is 256 pW, while its read and write power consumption are 6 µW and 1.9 µW, respectively. Also, the cell is half select disturbance-free and therefore supports bit-interleaving. This ensures the increased reliability for the cell. All the aforementioned merits for the cells are achieved with a minimal layout area of 0.553 µm2.

A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters

A novel loadless four-transistor static random access memory (4T SRAM) cell is proposed that consists of two N-type driver MOSFETs and two P-type access ones whose gate leakage currents from word-line are used for holding data in the cell. It is shown that the proposed cell has a higher tolerance for manufacturing device fluctuations compared with the conventional loadless 4T SRAM. Furthermore, it is free from bit-line disturb in contrast to the conventional cell. It is confirmed by simulation in 32 nm technology node that the read static noise margin (SNM) of the proposed cell reaches 138.7% of the six-transistor SRAM cell and that the hold SNM can be acceptable when the gate insulator thickness of the P-type access MOSFETs is made thinner than the N-type driver MOSFETs. The retention current for the proposed cell decreases to 66.7% of the 6TSRAM and the data rate in read increases to 125%.

A Nonvolatile 7T2M SRAM Cell with Improved Noise Margin for Energy Efficient In Memory Boolean Computations

The current computing systems are facing von Neumann bottleneck (VNB) in modern times due to the high prominence on big-data applications such as artificial intelligence and neuromorphic computing. In-memory computation is one of the emerging computing paradigms to mitigate this VNB. In this paper, a memristor-based robust 7T2M Nonvolatile-SRAM (NvSRAM) is proposed for energy-efficient In-memory computation. The 7T2M NvSRAM is designed using CMOS and memristor with a higher resistance ratio, which improved the write margin by 74.44% and the energy consumption for read and write operation by 5.10% and 9.66% over conventional 6T SRAM at the cost of increment in write delay. The read decoupled path with the VGND line enhances the read margin and read path Ion/Ioff ratio of 7T2M NvSRAM cell by 2.69× and 102.42%, respectively over conventional 6T SRAM. The proposed cell uses a stacking transistor to reduce the leakage power in standby mode by 64.20% over conventional 6T SRAM. In addition to the normal SRAM function, the proposed 7T2M NvSRAM performs In-Memory Boolean Computation (IMBC) operations such as NAND, AND, NOR, OR, and XOR in a single cycle without compute-disturb (stored data flips during IMC). It achieves 4.29-fJ/bit average energy consumption at 1.8 V for IMBC operations

6T and 8T SRAM Cell Simulation with Power Loss Analysis

Reducing the power consumption in a VLSI circuits is a prime concern now a days. Memory circuits play an important role in the design of electronic small power devices. Almost every digital systems is having memory as an important part in their design. The high speed circuits dissipate a considerable amount of power in a short time. In this paper conventional SRAM cell is modified little bit to reduce the dynamic power dissipation. The overall capacitance reduced by adding few extra transistors. Because of the fact that charging and the discharging of the bit lines consumes the most power , so 6T cell and 8T cell can be used to reduce the power by adding an extra number of transistors to the pull down path. In this paper 6T SRAM cell as well as 8T SRAM cell simulated and their performance compared in terms of power dissipation.

A low‐leakage single‐bitline 9T SRAM cell with read‐disturbance removal and high writability for low‐power biomedical applications

AbstractThe design of power‐efficient SRAM cells is necessary for biomedical applications such as body area networks (BANs) to extent their battery life. SRAM cell's power consists of two main components, including leakage power and dynamic power, in which the former overcomes the latter in advanced technology. This paper presents a low‐leakage single‐bitline 9T (L2SB9T) SRAM cell. The proposed design is free from read‐disturbance issue and eliminates writing “1” problem. The results are carried out by utilizing HSPICE and 16‐nm CMOS PTM at a 0.7 V, 25°C, and under severe PVT variations. The proposed L2SB9T SRAM cell is comprehensively compared with other recently published SRAM cells including conventional 6T, write/read enhanced 8T (WRE8T), transmission‐gate 9T (TG9T), read‐disturb‐free 9T (RDF9T), fully differential 10T (Chang10T), data‐independent read port 10T (DIRP10T), and single‐bitline 11T (SB11T). It shows at least 1.26X/1.07X/1.01X improvement in read static noise margin (RSNM)/write static noise margin (WSNM)/write margin (WM). Furthermore, the leakage power is reduced by the proposed cell, at least 1.137X. Moreover, the suggested cell consumes the third/second best dynamic read/write power, which is 1.42X/1.37X lower than that of conventional 6T SRAM cell. The proposed L2SB9T SRAM cell performs its read/write operation reliably by showing at least 1.71X narrower speared in RSNM compared to the best SRAM cell and third best WM variability. For all these improvements, the proposed L2SB9T SRAM cell incurs a 4.20X/1.06X/1.808X penalty in read delay/write delay/layout area when compared with the best SRAM cells, that is, the Chang10T/6T/6T.

A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application

A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application

Design and Implementation of Array for Scaling Power and Area in 4t SRAM Cell

Design and Implementation of Array for Scaling Power and Area in 4t SRAM Cell

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10,100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

Thermal Stability Analysis of Single-Ended 9T-ST Robust SRAM Cell for Near-Threshold Operation

This paper presents a single-ended Schmitt Trigger-based 9T SRAM cell, significantly improving thermal stability for real-time memory applications on a chip operated in a high radiation environment. The proposed single-ended 9T-ST SRAM cell has 73% and 13% improvement in read stability, 42% and 13% improvement in hold stability from 6T and 10T SRAM cells, respectively. The read stability of the proposed SRAM cell is compared with the conventional 6T SRAM cell, which is designed and tested for 23000 MC simulation samples to protect it from read failure. During read operation, the impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for a temperature change from 20∘C to 60∘C, as 5%, 32%, and 48% variation in RSNM for 9T-ST, 10T-ST, and 6T SRAM cells, respectively. The proposed SRAM cell is designed and verified in the Synopsys Custom compiler.

A 9T FinFET SRAM cell for ultra-low power application in the subthreshold regime

Due to the scaling of the CMOS, the limitations of these devices raised the need for alternative nano-devices. Various devices are proposed like FinFET, TFET, CNTFET. Among these, the FinFET emerges as one of the promising devices which can replace the CMOS due to its low leakage in the nanometer regime. The electronics devices are nowadays more compact and efficient in terms of battery consumption. The CMOS SRAMs have been replaced by the FinFET SRAMs due to the scaling limitations of the CMOS. Two FinFET SRAM cells have been which power efficient are and having high stability. Performance comparison of these cells has been done to analyze the leakage power and the static noise margins. The simulation of the cells is done at 20 nm FinFET technology. It has been analyzed that the write margin of improved 9T SRAM cell achieves an improvement of 1.49x. The read margin is also showing a drastic improvement over the existing cells which has been compared in the paper. The hold margin was found to be better in the case of the proposed SRAM cell at 0.4 V. The gate length has been varied to find the effect on read margin with gate length.

Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements

The machine learning and convolutional neural network (CNN)-based intelligent artificial accelerator needs significant parallel data processing from the cache memory. The separate read port is mostly used to design built-in computational memory (CRAM) to reduce the data processing bottleneck. This memory uses multi-port reading and writing operations, which reduces stability and reliability. In this paper, we proposed a self-adaptive 12T SRAM cell to increase the read stability for multi-port operation. The self-adaptive technique increases stability and reliability. We increased the read stability by refreshing the storing node in the read mode of operation. The proposed technique also prevents the bit-interleaving problem. Further, we offered a butterfly-inspired SRAM bank to increase the performance and reduce the power dissipation. The proposed SRAM saves 12% more total power than the state-of-the-art 12T SRAM cell-based SRAM. We improve the write performance by 28.15% compared with the state-of-the-art 12T SRAM design. The total area overhead of the proposed architecture compared to the conventional 6T SRAM cell-based SRAM is only 1.9 times larger than the 6T SRAM cell.