A Nonvolatile 7T2M SRAM Cell with Improved Noise Margin for Energy Efficient In Memory Boolean Computations

Abstract

The current computing systems are facing von Neumann bottleneck (VNB) in modern times due to the high prominence on big-data applications such as artificial intelligence and neuromorphic computing. In-memory computation is one of the emerging computing paradigms to mitigate this VNB. In this paper, a memristor-based robust 7T2M Nonvolatile-SRAM (NvSRAM) is proposed for energy-efficient In-memory computation. The 7T2M NvSRAM is designed using CMOS and memristor with a higher resistance ratio, which improved the write margin by 74.44% and the energy consumption for read and write operation by 5.10% and 9.66% over conventional 6T SRAM at the cost of increment in write delay. The read decoupled path with the VGND line enhances the read margin and read path Ion/Ioff ratio of 7T2M NvSRAM cell by 2.69× and 102.42%, respectively over conventional 6T SRAM. The proposed cell uses a stacking transistor to reduce the leakage power in standby mode by 64.20% over conventional 6T SRAM. In addition to the normal SRAM function, the proposed 7T2M NvSRAM performs In-Memory Boolean Computation (IMBC) operations such as NAND, AND, NOR, OR, and XOR in a single cycle without compute-disturb (stored data flips during IMC). It achieves 4.29-fJ/bit average energy consumption at 1.8 V for IMBC operations