4-inch Si Wafer Research Articles

Improvement of imaging performance of silicon micropore X-ray optics by ultra long-term annealing.

We have been developing a light-weight X-ray telescope using micro electro mechanical systems technologies for future space missions. Micropores of 20 µm width are formed in a 4-inch Si wafer with deep reactive ion etching, and their sidewalls are used as X-ray reflection mirrors. The flatness of the sidewall is an important factor to determine the imaging performance, angular resolution. It is known that hydrogen annealing is effective to smooth a Si surface. We tested 150 hour annealing to achieve the ultimately smooth sidewalls. After 50 hour, 100 hour, and 150 hour annealing, the angular resolution improved 10.3, 4.0, and 2.6 arcmin in full width at half maximum (FWHM) and 17.0, 14.5, and 10.8 arcmin in half-power width (HPW). In spite of this improvement, the edge shapes of the sidewall were rounded. Therefore, both edges of the sidewall were ground and polished, and then the angular resolution was improved further to 3.2 arcmin (FWHM) and 5.4 arcmin (HPW).

Large area microwave plasma CVD of diamond using composite right/left-handed materials

Diamond growth at low temperatures (≤400 °C) and over large areas is attractive for materials, which are sensitive to high temperatures and require good electronic, chemical or surface tribological properties. Resonant-cavity microwave plasma enhanced (MWPE) chemical vapor deposition (CVD) is a standard method for growing diamonds, however, with limited deposition area. An alternative method for CVD of diamond over large area and at low temperature is to use a surface wave plasma (SWP). In this work we introduce a novel method to excite SWP using composite right/left-handed (CRLH) materials and demonstrate growth of nanocrystalline diamond (NCD) on 4-inch Si wafers. The method uses a set of slotted CRLH waveguides coupled to a resonant launcher, which is connected to a deposition chamber. Each CRLH waveguide supports infinite wavelength propagation and consists of a chain of periodically cascaded unit cells. The SWP is excited by a set of slots placed to interrupt large area surface current on the resonant launcher. This configuration yields a uniform gas discharge distribution. We achieve 80 nm/h growth rate for NCD films with a low surface roughness (5–10 nm) at 395 °C and 0.5 mbar pressure using a H2/CH4/CO2 gas mixture.

Investigation for Low-Rate Fenceless Al Etching Applied in Fabrication of Superconducting Circuits

Ion beam etching (IBE) is introduced in the fabrication process developed from Nb03 in SIMIT, for the etching of Al-AlOx layer. However, we found that IBE creates fences at the edges of etched profiles because of redeposition of the Al. To solve this problem, we systematically investigated the yield of fenceless patterns and the junction quality as a function of ion beam incidence angle. The yield increases as the incidence angle decreases, 0° causing the least fence formation. The yield dependence was explained by a fence formation model developed from a two-dimensional redeposition algorithm. Given that the un-etched foots due to the shadow effect become visible as angle decreases, the optimal condition is finally set to be 400 eV with incidence angle of 10°. Nb/Al-AlOx/Nb junctions fabricated by Al-AlOx layer etching at incidence angle of 10° showed good junction quality with a low subgap leakage current. We could also obtain a high yield of shunted and unshunted Nb/Al-AlOx/Nb junctions with the minimum size of 1.4 μm in diameter on 4-inch Si wafers. These results prove the feasibility to achieve fabrication without anodization process and patterning of Al to improve the reliability.

Multi-wafer-scale growth of WSe2 films using a traveling flow-type reactor with a remote thermal Se cracker

Two-dimensional (2D) transition metal dichalcogenides (TMDCs) have demonstrated superior electrical and optical characteristics and are expected to replace silicon in semiconductor materials. However, in practice the use of TMDCs remains a challenge due to the lack of a suitable method for the large-scale synthesis of TMDCs. Herein we demonstrated a multi-wafer-scale growth method to obtain very uniform and continuous 2D WSe2 films by combining the selenization of the W metal using thermally cracked Se molecules, a metal-agglomeration-suppressed growth technique, and a traveling flow-type reactor. The usefulness of the traveling flow reactor must be attributed to the self-saturated selenization of a very thin W metal precursor film on a large-area substrate. The number of 2D WSe2 layers was easily controlled by varying the thickness of the W precursor. Raman scattering and thickness measurements showed that WSe2 films grew uniformly on three 4-inch Si wafers at once, at both 530 and 600 °C. The average Hall mobility and carrier concentration of 6-nm-thick p-type WSe2 films on the three wafers were 22.8 cm2 V−1 s−1 and 3.69 × 1016 cm−3, respectively. The field effect (FE) transistor with the 6-nm WSe2 channel and SiO2 back gate insulator also showed p-type transfer characteristics. The formation of a WSe2/MoSe2 vertical heterostructure also demonstrated the usefulness of the method proposed herein.

High-performance and scalable metal-chalcogenide semiconductors and devices via chalco-gel routes.

We report a general strategy for obtaining high-quality, large-area metal-chalcogenide semiconductor films from precursors combining chelated metal salts with chalcoureas or chalcoamides. Using conventional organic solvents, such precursors enable the expeditious formation of chalco-gels, which are easily transformed into the corresponding high-performance metal-chalcogenide thin films with large, uniform areas. Diverse metal chalcogenides and their alloys (MQ x : M = Zn, Cd, In, Sb, Pb; Q = S, Se, Te) are successfully synthesized at relatively low processing temperatures (<400°C). The versatility of this scalable route is demonstrated by the fabrication of large-area thin-film transistors (TFTs), optoelectronic devices, and integrated circuits on a 4-inch Si wafer and 2.5-inch borosilicate glass substrates in ambient air using CdS, CdSe, and In2Se3 active layers. The CdSe TFTs exhibit a maximum field-effect mobility greater than 300 cm2 V-1 s-1 with an on/off current ratio of >107 and good operational stability (threshold voltage shift < 0.5 V at a positive gate bias stress of 10 ks). In addition, metal chalcogenide-based phototransistors with a photodetectivity of >1013 Jones and seven-stage ring oscillators operating at a speed of ~2.6 MHz (propagation delay of < 27 ns per stage) are demonstrated.

Large-area and highly uniform carbon nanotube film for high-performance thin film transistors

Carbon nanotube thin film transistors (CNT-TFTs) are a potential TFT technology for future high-performance macroelectronics. Practical application of CNT-TFTs requires the production of large-area, highly uniform, density-controllable, repeatable, and high-throughput CNT thin films. In this study, CNT films were fabricated on 4-inch Si wafers and 2.5th generation (G2.5) backplane glasses (370 mm × 470 mm) by dip coating using a chloroform-dispersed high-purity semiconducting CNT solution. The CNT density was controlled by the solution concentration and coating times, but was almost independent of the substrate lifting speed (1–450 mm·min−1), which enables high-throughput CNT thin film production. We developed an image processing software to efficiently characterize the density and uniformity of the large-area CNT films. Using the software, we confirmed that the CNT films are highly uniform with coefficients of variance (CV) < 10% on 4-inch Si wafers and ∼ 13.8% on G2.5 backplane glasses. High-performance CNT-TFTs with a mobility of 45–55 cm2·V−1·s−1 were obtained using the fabricated CNT films with a high-performance uniformity (CV ≈ 11%–13%) on a 4-inch wafer. To our knowledge, this is the first fabrication and detailed characterization of such large-area, high-purity, semiconducting CNT films for TFT applications, which is a significant step toward manufacturing CNT-TFTs.

Wafer-scale fabrication of high-aspect ratio nanochannels based on edge-lithography technique

This paper introduced a wafer-scale fabrication approach for the preparation of nanochannels with high-aspect ratio (the ratio of the channel depth to its width). Edge lithography was used to pattern nanogaps in an aluminum film, which was functioned as deep reactive ion etching mask thereafter to form the nanochannel. Nanochannels with aspect ratio up to 172 and width down to 44 nm were successfully fabricated on a 4-inch Si wafer with width nonuniformity less than 13.6%. A microfluidic chip integrated with nanometer-sized filters was successfully fabricated by utilizing the present method for geometric-controllable nanoparticle packing.

탄소나노튜브의 저온성장을 위한 합성가스의 최적화 연구

This study investigated the growth characteristics of carbon nanotubes (CNTs) by changing a period of annealing time and a <TEX>$C_{2}H_{2}/H_2$</TEX> flow ratio at temperature as low as <TEX>$450^{\circ}C$</TEX> with inductively coupled plasma chemical vapor deposition. The 1-nm-thick Fe-Ni-Co alloy thin film served as a catalyst layer for the growth of CNTs, which was thermally evaporated on the 15-nm-thick Al underlayer deposited on the 50-nm-thick Ti diffusion barrier. The annealing at low temperature of <TEX>$450^{\circ}C$</TEX> brought about almost no granulation of the catalyst layer, and the CNT growth was not affected by a period of annealing time. A study of changing the flow rate of <TEX>$C_{2}H_{2}$</TEX> and <TEX>$H_2$</TEX> showed that as the ratio of the <TEX>$C_{2}H_{2}$</TEX> flow rate to the <TEX>$H_2$</TEX> flow rate was lowered, the CNTs were grown to be longer With further decreasing the flow ratio, the length of CNTs reached the maximum and then became shorter. Under the optimized gas flow rates, we successfully synthesized CNTs with a uniform length over a 4-inch Si wafer at <TEX>$450^{\circ}C$</TEX>.

FABRICATION AND PROPERTIES OF METAL-PZT-METAL CAPACITORS BY LIQUID DELIVERY MOCVD

ABSTRACT Pb(Zr1−x,Tix)O3(PZT) thin films were prepared on 8-inch and 4-inch Pt or Ir-electroded Si wafers by liquid delivery metal-organic chemical vapor deposition (LD-MOCVD) using cocktail sources of Pb, Zr and Ti. The processing conditions were optimized in order to obtain high-performance PZT films. The thickness uniformity of PZT films on 8-inch substrate was about ± 3.24%. The deposition rate of Pb (15.8 nm/min) and Ti (17.9 nm/min) deposited on Si substrate were faster than that of Zr (2.5 nm/min). The growth temperature of PZT film was adjusted to 570–630°C depending on the substrates used. The properties of metal/PZT/metal capacitors were also studied. The PZT films based on Pt substrate showed no good ferroelectric properties. By contrast, the ferroelectric properties of Ir/IrO2/PZT/IrO2/Ir capacitors were excellent. At an applied voltage of 5 V, the remanent polarization (Pr) and coercive field (Ec) values were about 36 μ C/cm2 and 50 kV/cm, respectively.

Deflection of wafers and cantilevers with Pt/LNO/PZT/LNO/Pt/Ti/SiO 2 multilayered structure

The present paper describes a Pt/LNO/PZT/LNO/Pt/Ti/SiO 2 multilayers deposited on 4-inch Si wafers. We have evaluated the variation of the deflection of the Si wafers with deposition of each of the thin films. The deposition of the multilayers has resulted in downward deflection (center is higher than edge) of the Si wafers. The multilayers have been also deposited onto SOI wafers and fabricated into piezoelectric micro cantilevers through MEMS bulk micromachining. The micro cantilevers have shown the upward deflection. We have characterized the ferroelectric and piezoelectric properties of the PZT thin films through electrical tests of the micro cantilevers. The dielectric constant, saturation polarization, remanent polarization and coercive field were measured to be 1050, 31.3 μC/cm 2, 9.1 μC/cm 2 and 21 kV/cm, respectively. The transverse piezoelectric constant, d 31, was measured to be − 110 pm/V from the DC response of the micro cantilevers.

Nitrogen‐Doped Tungsten Oxide Nanowires: Low‐Temperature Synthesis on Si, and Electrical, Optical, and Field‐Emission Properties

Very dense and uniformly distributed nitrogen-doped tungsten oxide (WO(3)) nanowires were synthesized successfully on a 4-inch Si(100) wafer at low temperature. The nanowires were of lengths extending up to 5 mum and diameters ranging from 25 to 35 nm. The highest aspect ratio was estimated to be about 200. An emission peak at 470 nm was found by photoluminescence measurement at room temperature. The suggested growth mechanism of the nanowires is vapor-solid growth, in which gaseous ammonia plays a significant role to reduce the formation temperature. The approach has proved to be a reliable way to produce nitrogen-doped WO(3) nanowires on Si in large quantities. The direct fabrication of WO(3)-based nanodevices on Si has been demonstrated.

137 Fabrication and Microstructure Analysis of Pt/C Multilayers for X-ray Optics

Pt/C multilayer film with d-spacing of about 4nm and 30 bilayers has been deposited by the ion beam sputtering process on commercially available 4-inch Si wafer substrates. The x-ray reflectivity of the fabricated film was evaluated using the W-Lα x-ray (λ=0.148nm) with the incident angle 0&acd;2.5 deg. The reflectivity of the first Bragg peak was 58.2%, which was 87.8% of calculated optimum value. The interface roughness of the multilayers derived from the x-ray measurement was 0.229nm rms. High-resolution transmission electron microscope observations and selected area electron diffraction studies indicate that the multilayer consists of amorphous carbon layers and polycrystalline platinum layers. The microscope observation showed the interface roughness of Pt/C multilayers were mainly originated in the size and alignment of the Pt crystallites.

Metal Organic Chemical Vapor Deposition of (Ba,Sr)RuO 3 Conductive Oxide Film for (Ba,Sr)TiO 3

(Ba,Sr)RuO 3 films have been tailored as an electrode for (Ba,Sr)TiO 3 which is a promising material for the high dielectric in ULSI DRAM. In this study, BSR conductive oxide film was deposited on 4-inch Si-wafer by metal organic chemical vapor deposition (MOCVD) using single cocktail source for the practical device application. Liquid delivery system (LDS) and vaporization cell were utilized for the delivery and vaporization of single cocktail source, respectively. The source feeding rate was controlled by liquid mass flow controller(LMFC). Ba(METHD) 2 , Sr(METHD) 2 , Ru(METHD) 3 precursors and solvent [n-butylacetate(C 6 H 12 O 2 )] were mixed for single coctail source. Among the various deposition parameters, control of the oxygen flow rate turned out to be crucial for determining the phase formation, resistivity, and the composition ratio of (Ba,Sr)RuO 3 films. Highly (110)-textured (Ba,Sr)RuO 3 film was obtained when Ar/O 2 ratio was 100/300sccm with the source flow rate of 0.075sccm. Oxygen annealing of (Ba,Sr)RuO 3 films enhanced the properties of the films without changing the (110) texture, and the resistivity of the resulted film was 2440 w z cm.

Metal Organic Chemical Vapor Deposition of (Ba,Sr)RuO 3 Conductive Oxide Film for (Ba,Sr)TiO 3

(Ba,Sr)RuO 3 films have been tailored as an electrode for (Ba,Sr)TiO 3 which is a promising material for the high dielectric in ULSI DRAM. In this study, BSR conductive oxide film was deposited on 4-inch Si-wafer by metal organic chemical vapor deposition (MOCVD) using single cocktail source for the practical device application. Liquid delivery system (LDS) and vaporization cell were utilized for the delivery and vaporization of single cocktail source, respectively. The source feeding rate was controlled by liquid mass flow controller(LMFC). Ba(METHD) 2 , Sr(METHD) 2 , Ru(METHD) 3 precursors and solvent [n-butylacetate(C 6 H 12 O 2 )] were mixed for single coctail source. Among the various deposition parameters, control of the oxygen flow rate turned out to be crucial for determining the phase formation, resistivity, and the composition ratio of (Ba,Sr)RuO 3 films. Highly (110)-textured (Ba,Sr)RuO 3 film was obtained when Ar/O 2 ratio was 100/300sccm with the source flow rate of 0.075sccm. Oxygen annealing of (Ba,Sr)RuO 3 films enhanced the properties of the films without changing the (110) texture, and the resistivity of the resulted film was 2440 w z cm.

Synthesis of nanocrystalline diamond films using microwave plasma CVD

Diamond is one of the most valuable materials for the industrial applications because of its excellent properties including high hardness, with good electrical insulation and thermal conductivity. Mechanical polishing processes of diamond are difficult and very costly. To limit those costs, it is reasonable to think that the surface roughness of the as-grown diamond film should be as small as possible. In this study, a nanocrystalline diamond film was synthesized on a 4-inch Si wafer at 923 K and methane concentration of 10 vol.%, (H 2/CH 4=100/10 sccm) using a microwave plasma CVD system. In order to increase the nucleation density, the substrate was pretreated by dry scratch method with diamond powder of two sizes (250 nm and 5 nm). The nucleation density was approximately 1×10 11 cm −2. The grown diamond films were analyzed by Raman spectroscopy and X-ray diffraction (XRD). The grain size was observed to be approximately 10 nm by FE-SEM observation. Surface roughness was measured as Rms=8.4 nm by atomic force microscope (AFM). The as-grown properties of those nanocrystalline diamond films were almost efficient for tribological and the optical applications.

The preparation of (001) textured diamond films with large areas

The (001)-textured diamond films were deposited on a 4-inch Si wafer by a three-step method. First, fine diamond powder was seeded on the substrate by a dipping method to obtain high diamond nuclei density and low interface state density. Then a H ion etching and annealing was performed for 1 h by setting an electric potential of −120 V to improve the adhesion between diamond and substrate and obtain high (001)-textured films. At last, diamond films were deposited under the condition for (001)-textured growth. A SEM was used to analyze the morphology of diamond crystallites and the film formed with the above three steps and Raman spectra was applied to obtain the phase purity of the films. The results show that large area, low interface state density, uniform and (001)-textured diamond films can be synthesized by this three-step process.

Nanotechnology and Model Catalysis: The Use of Photolithography for Creating Active Surfaces

New and very stable model catalysts have been developed. Two types of samples on oxidized 4-inch wafers were produced using processes that are generally employed in semiconductor device technology. A single wafer exhibits 109 to 1010 active sites on an otherwise flat silicon oxide surface. Sputter etching of a number of bilayers (Pd/SiO2), stacked on an oxidized Si wafer surface resulted in billions of isolated towers, consisting of disks of active metal layers, separated by inert substrate material. A second system was produced by etching pits into a heavily oxidized 4-inch Si wafer. Active material was deposited into the pits by e-beam evaporation or spin-coating of precursor solutions. The topography and chemical composition, and the changes induced by the reaction conditions applied, including stability and chemical behavior of the nanostructured systems, were investigated by means of AFM, SEM, temperature-programmed methods and XPS.

Spatial Uniformity of the Mechanical Properties of 3C-SiC Films Grown on 4-Inch Si Wafers as a Function of Film Growth Conditions

Spatial Uniformity of the Mechanical Properties of 3C-SiC Films Grown on 4-Inch Si Wafers as a Function of Film Growth Conditions

Self-Aligned Epitaxial Cosi2 Formation From Multilayer Co/Ti-Si(100) by a Two-Step Rta Process

ABSTRACTWe have extended our recent work on nano-scale CoSi2 formation from Co/Ti(O)multilayers on Si(100) to a self-aligned epitaxial CoSi2 structure produced by a two-step RTA annealing process. Parallel oxide stripes/Si windows were produced on a 4-inch Si(100) wafer by thermal oxidation and patterning. Six layers of 20nm Co and 10nm Ti were deposited sequentially on the patterned wafers with Ti as the first layer. The wafers were then annealed at 550°C to 700°C in N2 using a lamp RTA system. XTEM and RBS showed that a 25nm CoSi layer formed at the interface after a 650°C, 60sec annealing. The unreacted layers above it and oxide were selectively removed leaving a residual amorphous layer and CoSi intact on the patterned Si substrates. A second annealing at 900'C for 10sec produced 20nm of epitaxial CoSi2 covered with an ∼10nm CoxTiy(O)Siz surface layer. The epitaxial CoSi2 layer was thermally stable up to 1000°C, had a resistivity of ∼20μΩ-cm, and consumed ∼300Å of Si, thereby satisfying the most stringent deep submicron device contact scaling requirements.

Low-Temperature Heteroepitaxy of β-SiC on Si (111) Substrates

AbstractWe developed a heteroepitaxial growth technique for large-area β-SiC films on Si substrates without buffer layers at 850ºC and 1000ºC. The substrates were vicinal 4-inch (111) Si wafers. The β-SiC films had smooth surfaces and were crack-free. X-ray diffraction and electron diffraction analysis revealed that the films grown at 1000ºC were single crystals. Satisfactory characteristics were obtained in aMOSFET with a β-SiC/Si02/poly-Si substrate structure. Our evaluations indicate that the β-SiC films were high-quality crystals.