1-bit Full Adder Research Articles

Performance evaluation of an efficient five input majority gate design in QCA nanotechnology

Quantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design.

Implementation of Low Power High Speed Adder’s using GDI Logic

Addition is a vital arithmetic operation and is the base of other arithmetic operations such as multiplication, subtraction and division. Adder is a digital circuit that does addition of binary numbers. The 1-bit full adder is the basic block of an arithmetic unit. In VLSI, there are many efficient techniques to design digital circuits. Some of the techniques are Pass Transistor logic (PTL), Complementary metal oxide semiconductor (CMOS) and Transmitter gate (TG). There are several adder designs implemented to reduce the power. However, each design undergoes from precise disadvantage. The adder design with good driving capability requires more power and the design with more delay which consumes less power. In this paper 8-bit Carry Increment Adder (CIA), Carry Bypass Adder (CBA), Carry Skip Adder (CSKA), Carry Look Ahead Adder (CLA), Kogge Stone Adder (KSA), Han Carlson Adder (HCA), and Brent Kung Adder (BKA) are implemented using Gate Diffusion Input (GDI) logic. These designs are simulated and implemented using Tanner tool. The result shows that CBA, CLA, and KSA designs using GDI logic are more efficient compared to CMOS logic in view of power consumption, delay, and area (transistors count) respectively.

Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis

The difficulties which the CMOS technology is facing at the nano scale has led to the investigation of quantum-dot cellular automata (QCA) nanotechnology and reversible logic as an alternative to conventional CMOS technology. In this paper, these two paradigms have been combined. Firstly, a new 3 × 3 reversible gate, SSG-QCA, which is universal and multifunctional in nature, is proposed and implemented in QCA using conventional 3-input majority voter based logic. By using the concept of explicit interaction of cells, the proposed gate is further optimized and then used to design an ultra-efficient 1-bit full adder in QCA. The universal nature has been verified by designing all the logic gates from the proposed SSG-QCA gate whereas the multifunctional nature is verified by implementing all the 13 standard Boolean functions. The proposed 3 × 3 gate and adder designs are then extensively compared with the existing literature and it is observed that the proposed designs are ultra-efficient in terms of both area and cost in QCA technology. In addition to this energy dissipation analysis for different scenarios is also done on all the designs and it is observed that the proposed designs dissipate minimum energy thereby making them suitable for ultra-low power designs.

New 3-D CMOS Fabric With Stacked Horizontal Nanowires

As 2-D CMOS reaches its fundamental scaling limits due to device, manufacturing, and interconnect bottleneck related constraints at the nanoscale, migration to 3-D provides a possible alternative to continue technology scaling in future. Toward that goal, several 3-D integration approaches with multi-die, multichip, and sequential layers stacking are pursued. However, these approaches only show incremental density benefits and exhibit new challenges, such as lack of thermal management, increasing cost, and reliability issues. In contrast to these, we proposed a radically different fabric concept, called stacked horizontal nanowire-based 3-D CMOS (SN3D), on a single die that can offer a paradigm shift in technology scaling as well as design. Using prefabricated and doped stacked horizontal nanowires as fundamental building blocks, the fabric is assembled using architected connectivity and insulation features. Innovations in circuit style for mapping to SN3D’s physical framework, and bottom-up material filling-based manufacturing techniques are also central to our approach. In this paper, we detail, fabric’s core constructs, logic circuits implementation in SN3D fabric, benchmarking methodology and results, and finally the manufacturing aspects. Our circuit analysis reveals tremendous benefits; for a 4-bit full adder design, SN3D shows $11\times $ , 19%, 18%, and 6.7 $\times $ , 8.69%, 9% benefits over state-of-art 2-D CMOS and transistor-level monolithic 3-D in terms of density, power, and performance, respectively. In addition, our step-by-step TCAD emulation of manufacturing flow establishes feasibility. If realized, the SN3D fabric can be transformative for the semiconductor industry.

Two novel inverter-based ternary full adder cells using CNFETs for energy-efficient applications

ABSTRACTCarbon nanotube field effect transistors (CNFETs) exhibit great promise and extensions to silicon MOSFET due to their excellent electronic properties and extremely small size. Implementable CNFET circuits have operational characteristics to approach the advantage of using multiple-valued logic (MVL) in voltage mode. In MVL implementation computation for the system will be faster than the binary system with improved density of digital circuits. This paper presents two novel 1-bit inverter-based ternary full adder cells which second design cell uses only 37 CNFET transistors in its structure. These designs have been proposed using a new definition of Majority-not based full adder, and are compared to the other adders based on power consumption, speed and power-delay product (PDP). Proposed designs are evaluated using simulation run on HSPICE with 32 nm CNFET standard technology under various operational conditions, including different supply voltages, output load variation and different operating temperatures. According to simulation results, all proposed ternary full adder designs in compare to the state of the art circuits in literature have been demonstrated up to 81% and 80%, respectively, improvement in power consumption and PDP.

Analysis on Circuit Metrics of 1-Bit FinFET Adders Realized using Distinct Logic Structures

Objective: To compare and analyse different FinFET full adder circuits by varying the temperature. Method/Analysis: A 1-bit full adder is designed using various logic styles and the performance of these adders are compared over a range of temperature values. 32nm FinFET Predictive Technology Model (PTM) is used for designing purpose. Various logic design styles utilised are Complementary Metal-Oxide Semiconductor (CMOS) logic, Transmission Gate (TG) logic, Complementary Pass-Transistor (CPTL) logic, Gate Diffusion Input (GDI) logic. Cadence Virtuoso and Spectre are used for designing and simulation purpose, respectively. Findings: The performance of these adders are analysed based on key circuit metrics like static power, dynamic power, leakage power, delay and power delay product (PDP). On comparison, it is evident that the GDI based adder consumes less leakage power. Also, the propagation delay and power delay product is very less in GDI adder. Novelty/Improvements: The simulation results prove that the GDI adder structure outperforms other structures in sub nanometer technology. This advantage makes GDI technology suitable for realisation of combinational circuits. Future research in digital circuits can be carried out by using GDI technology for designing low power and compact integrated circuit design. Keywords: Complementary Pass-Transistor, Delay, FinFET, Gate Diffusion Input, Leakage Power, Low Power Adder, Transmission Gate, CMOS

Ultra‐low‐voltage GDI‐based hybrid full adder design for area and energy‐efficient computing systems

In recent years, ultra-low-voltage (ULV) operation is gaining more importance for achieving minimum energy consumption. Full adder is the basic computational arithmetic block in many of the computing and signal/image processing applications. Here, a new hybrid 1-bit full adder circuit which employs both Gate Diffusion Input (GDI) logic and multi-threshold voltage (MVT) transistor logic is reported. The main objective of the proposed MVT-GDI-based hybrid full adder design is to provide minimum energy consumption with less area. The proposed hybrid design is simulated using standard 45 nm CMOS process technology at an ULV of 0.2 V. The post-layout simulation results have shown that the proposed design achieved significant improvements in comparison with the other reported designs by achieving >57%, 92% savings in the Energy and EDP, respectively, with only 14 transistors. Monte–Carlo simulations have also been performed and is found that the proposed design methodology yields full functionality and robustness against local and global process variations. Normalised energy metrics to 32 and 22 nm technologies shows that the proposed design achieves >57% energy savings in prior to the recent works.

Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology

In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of supply. The result showed the reduction of VBB technique in term of peak power, and average power, compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.

Compact Modeling of Perpendicular-Magnetic-Anisotropy Double-Barrier Magnetic Tunnel Junction With Enhanced Thermal Stability Recording Structure

As the basic storage unit of spin transfer torque magnetic random-access memory (STT-MRAM), the perpendicular magnetic anisotropy (PMA) magnetic tunnel junction (MTJ) has been extensively studied in recent years. Lowering the critical switching current and improving the data retention are two crucial pathways to optimize the performance of STT-MRAM. However, the conventional MTJ can merely achieve both. In this paper, we present a physics-based compact model of Ta/CoFeB/MgO PMA double-barrier MTJ (DMTJ) with enhanced thermal stability recording structure. Combination of double-barrier and synthetic double-free layers can heighten the STT effect and enhance the thermal stability simultaneously. A larger STT switching efficiency, compared with conventional MTJ, can thus be realized. The modeling results show great agreement with experimental results. A 1-bit magnetic full adder (MFA) based on DMTJ, as a hybrid logic-in-memory circuit example, has been designed and simulated to validate its functionality. This SPICE-compatible compact model will be useful for high-performance hybrid MTJ/CMOS circuit and system designs.

A Low Power - High Speed CNTFETs Based Full Adder Cell With Overflow Detection

The transformation from the development of enabling technology to mass production of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the product as implicit pre-cursors. The Carbon Nanotube Field Effect Transistor (CNFET) is the present day technology. In this manuscript, we have used CNFET as the enabling technology to design a 1-bit Full Adder (1b-FA16) with overflow detection. The proposed 1b-FA16 is designed using 16 transistors. Finally, the proposed 1b-FA16 is further used to design a Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) circuit and RCA with overflow bit detection. Methods and Results: The proposed 1b-FA16 circuit was designed with CNFET technology simulated at 32 nm with a voltage supply of +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM. Comparison of the existing full adder designs with the proposed 1b-FA16 design was done to validate the improvements in terms of power, delay and Power Delay Product (PDP). Table 2, shows the results of comparison for the proposed 1b-FA16 with the existing full adder designs implemented using CNFET for parameters like power, delay and power delay product. Conclusion: It can be concluded that the proposed 1b-FA16 yielded better results as compared to the existing full adder designs implemented using CNFET. The improvement in power, delay and power delay product was approximately 11%, 9% and 24% respectively. Hence, the proposed circuit implemented using CNFET gives a substantial rate of improvements over the existing circuits.

An efficient inexact Full Adder cell design in CNFET technology with high-PSNR for image processing

ABSTRACTThe design of inexact circuits at the transistor level remarkably improves figures of merits such as power consumption, delay, energy, and area. Therefore, inexact technique for designing circuits has attracted the attention of researchers worldwide. Designing inexact Full Adder cell as a building block of a variety of arithmetic circuits can affect the entire electronic system’s performance. In this paper, two novel inexact 1-bit Full Adder cells are presented using carbon nanotube field effect transistors (CNFETs). The capacitive threshold logic (CTL) is used to realize the proposed cells. Comprehensive simulations at two levels of abstraction, i.e., application and hardware are carried out to evaluate the efficacy of these circuits. First, the motion detector which is one of the image processing applications is deployed in MATLAB software to measure peak signal-to-noise ratio (PSNR) figure of merit. At hardware level, the HSPICE tool is used to carry out simulations and measure power, delay, power-delay product (PDP), energy-delay product (EDP), power-delay-area product (PDAP) and power-delay-area-PSNR product (PDAPP). Simulation results confirmed the superiority of the proposed Full Adder cells compared to others. For instance, the proposed 6TIFA improves PDAPP metric at least 21% and at most 76% compared to its counterparts at 0.9V power supply.

Design and software characterization of finFET based full adders

Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.

Reconfigurable logic for carry-out computing in 1-bit full adder using a single magnetic tunnel junction

We propose a method for reconfigurable logic using a single magnetic tunnel junction (MTJ) as the main computing element in the single-gate architecture. The introduction of the MTJ to reconfigurable computing provides advantages in layout efficiency, power consumption, and the device variation problem. In this study, we present a three-terminal MTJ implemented by two inputs (ampere magnetic field and spin torque-transfer current) acting as a logic element that performs the Boolean logic functions of NAND and NOR with corresponding programmable input values in a fixed architecture. In addition, the reconfigurable functionality is confirmed through demonstration of carry-out computing across the operator built with single-MTJ logic architecture.

Reconfigurable Boolean Logic in Memristive Crossbar: The Principle and Implementation

In-memory computing based on memristive logic is considered as a prospective non von Neumann computing paradigm. In this letter, we systematically analyze the four-variable logic method and map it into the operation of two anti-serial complementary memristors in the crossbar array architecture. Arbitrary Boolean logic can be implemented within three cycles with the experimental evidence of reconfigurable NAND, NOR, and XOR logic using Pt/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TiN devices. Taking advantage of the functional flexibility, a parallel 1-bit full adder that can be realized in 8 cycles within a 4 × 3 array has been designed and verified in simulation.

Implementation Topology of Full Adder Cells

Abstract Design of different complementary metal-oxide-semiconductor (CMOS) topologies of 1-bit full adder (FA) cell in terms of power, delay, power-delay-product (PDP) and energy-delay-product (EDP) have been analyzed for the application of the intelligent systems. The FA cells have been implemented with respect to the different CMOS topologies such as complementary-CMOS (C-CMOS), complementary pass-transistor logic (CPL), CMOS transmission gates (TGA), and CMOS transmission function (TFA) and simulated at 180 nm technology. The work has been extended to the comparison of FA cell implementation using the increasingly demanding ultra-thin-body silicon-on-insulator (UTBSOI) transistors. Based on the simulation results, the application of UTBSOI in the FA cell has resulted in 26.7%, 24.3%, 44.6% and 44.7% improvements over that of best design architecture reported in this literature in terms of power, delay, PDP, and EDP, respectively.

A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achieve reduction in leakage power and GBN up to 60% and 80%, respectively, as compared to the best reported approximate FA circuits. The modified approximate FA also achieves 83% reduction in leakage power as compared to conventional FA. Finally, application level metrics such as peak signal to noise ratio (PSNR) are considered to measure the performance of all the proposed approximate FAs.

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

ABSTRACTThis paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS.

A novel technique for static leakage reduction in 16 nm CMOS design

ABSTRACTA novel technique for static leakage reduction in CMOS technology is proposed in this paper. This technique uses high and low values of threshold voltage as well as high and low values of gate oxide width in the design. Hence, the proposed technique is named as Dual Threshold and dual Oxide for Static power reduction (DTOS). Simulation results have been carried out in a 3-input nand gate and 1-bit conventional full adder circuits using 16 nm CMOS technology. Comparison of the proposed technique, i.e. DTOS is done with some of the existing techniques of leakage reduction like multi-threshold CMOS (MTCMOS), dual-Vth and dual-Tox. The DTOS technique reduces an average of 75.4% of static power consumption as compared with MTCMOS, dual-Vth and dual-Tox approaches for leakage reduction for a 3-input nand gate. For a 1-bit full adder circuit, the novel technique reduces an average of 69.1% of the static power as compared to the above-mentioned techniques of power reduction. The delay of the proposed technique is increased with respect to MTCMOS technique whereas it is improved in other cases.

Implementation of Full Adder Using 5-Input Majority Gate

In this paper full adder was created employing five-input majority gate according to Quantum-Dot Cellular Automata (QCA) innovation. We used the QCA logic in our modified structure to reduce the delay. That report details the structure furthermore investigate associated with QCA dependent 1-bit full adder design for minimal energy purposes. This method permits decreasing energy expenditure, delay, additionally location involving electronic circuits.

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.