1-bit Full Adder Research Articles

Two new low-power Full Adders based on majority-not gates

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).

A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

In this paper a new low power and high performance adder cell using a new design style called “Bridge” is proposed. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP. We have performed simulations using HSPICE in a 90 nanometer (nm) standard CMOS technology at room temperature; with supply voltage variation from 0.65v to 1.5v with 0.05v steps.

Ultra high speed Full Adders

Two novel 1-bit Full Adder cells based on Majority Function and the similarity between the minterms of the Cout and Sum functions, are proposed. The cells offer higher speed and less Power-Delay Product (PDP) than the conventional and current implementations of the 1-bit Full Adder cells especially in low voltages. All the input patterns are used for simulation to obtain the delay and the power consumption parameters. Simulations demonstrate improvement in terms of PDP and significant improvement in terms of speed.

A Novel Multiplexer-Based Low-Power Full Adder

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.

A Comparison of Adiabatic Logic Circuit Techniques for an Energy Efficient 1-Bit Full Adder Design

Power dissipation has become a critical design constraint in portable applications like a hand held computer due to limited battery life and reliability of integrated circuits. In this paper, a detailed comparison of five adiabatic logic families is carried out by simulation using SPICE. The simulation results are obtained for full adders, which are designed using the different design techniques with a view to design an energy efficient 1-bit full adder. The parameters compared are average energy consumption per addition, instantaneous peak power dissipation, number of transistors required, and operating frequency range. Average energy consumption per addition of full adders is found to vary with the variation in power-clock as well as input signal frequencies. An optimum value of power-clock frequency at which minimum energy consumption occurs at a fixed input signal frequency is obtained for all circuit techniques. Full adders circuits are designed using 0.5 μm CMOS technology.

A Low Power Correlator for CDMA Wireless Systems

The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range ?7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer. As a ripple carry adder (RCA) consumes the least power among all the existing adder architectures, we have implemented the 4-bit adder as a RCA. Previous incrementers were implemented as ripple counters. In this paper we propose a novel incrementer which is faster than a ripple counter based incrementer. Hence, it can be operated at a reduced voltage resulting in considerable power reduction. The incrementer is implemented using multiplexers, AND gates and TSPC registers. The ripple-counter correlator and the proposed incrementer correlator were laid out in MAGIC using 0.5 μ CMOS technology followed by power estimation using HSPICE. It is shown that the proposed architecture requires 50% less power than a ripple counter based design.

Fabrication of GaAs-based integrated half and full adders by novel hexagonal BDD quantum circuit approach

Feasibility of a novel hexagonal binary decision diagram (BDD) quantum circuit approach based on Schottky wrap gate (WPG) control of GaAs/AlGaAs hexagonal nanowire network has been demonstrated through fabrication of half adders and full adders. Quantum BDD node devices were designed and realized utilizing WPG-controlled quantum wire (QWR) and single electron switches. BDD half sum and carry elements of a half adder were fabricated by integrating the WPG BDD node devices and they operated correctly through either quantum transport at low temperature or many electron classical transport at room temperature. Successful design of hexagonal BDD full adders for arbitrary bits on a hexagonal network without nanowire crossover and fabrication of QWR-based BDD 2-bit full adder on the AlGaAs/GaAs etched hexagonal nanowire network with node density of 10 7 cm −2 clearly indicated the capability of the present approach for large scale quantum device integration.

Performance analysis of low-power 1-bit CMOS full adder cells

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.

A low-complexity combinatorial RNS multiplier

A novel very large scale integration architecture and the corresponding design methodology for a combinatorial adder-based residue number system (RNS) multiplier are presented in this paper. The proposed approach to residue multiplier design, exploits the nonoccurring combinations of input bits to reduce the number of 1-bit full adders (FAs) required to compose an RNS multiplier. In particular, input bits which cannot be simultaneously asserted for any input residue value are organized into couples or triplets, which can be processed by OR gates instead of 1-bit adders, therefore reducing the RNS multiplier complexity. By comparing the performance and hardware complexity of the proposed residue multiplier to previously reported designs, it is found that the introduced architecture is more efficient in the area/spl times/time product sense. In fact, it is shown that a performance improvement in excess of 80% can be achieved in certain cases.

Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

In this paper, a new charge-recycling differential logic named split-level precharge differential logic (SPDL) is presented. It employs a new push-pull type output driver which is simple and separated from the NMOS logic tree. Therefore, it can improve energy efficiency, driving capability, and reliability compared with the previous differential logic structures which use cross-coupled inverters as the output driver. To verify the reliability and the applicability of the proposed SPDL in VLSI systems, an 8-bit full adder is fabricated in a 0.6-/spl mu/m CMOS technology. Experimental results show that the performance of the SPDL is about two times as good as that of the previous half-rail differential logic (HRDL) in terms of power-delay product. Moreover, the SPDL has stable operation under mismatch or parameter variation.

A synthesis methodology for ECL circuits based on mixed voltage-current representation

This paper presents a synthesis methodology for ECL circuits based on a mixed voltage-current signal representation and operation defined on the voltage and current signals. The ideas presented in this paper are then demonstrated on the design of an ECL 1-bit full adder. The paper concludes by presenting an algebraic system which is suitable for current signal representation and operation on currents.

A low-power compact switched output adiabatic logic (CSOAL) family

An improved low-power compact logic structure with a simple clock supply is presented. It is based on adiabatic switching principles. A comparison, made between the proposed structure and the previous structure, shows about 37% transistor count saving for the 1-bit full adder and 43% area saving for the 2-NAND/AND gate. HSPICE simulations validate that the power dissipations are at a comparable level with those of the previous adiabatic structure and are much lower than those of conventional static CMOS.

Extended phase-mode logic-circuits with resistive ground contact

We present extended phase-mode logic (EPL) circuits which have resistive ground contact. The phase-mode logic utilizes magnetic flux-transfer and is based on pulse propagation, i.e., it is one of single flux quantum systems. The proposed logic circuits of the EPL family can have the same ground reference, contrary to the original phase-mode circuits, Therefore, it is possible to couple different EPL elements on a single ground reference. Basic components of the EPL family (a phase-conserving branch, a phase-distributing branch, and an INHIBIT gate controlled by fluxon) are presented. The phase-distributing branch and the INHIBIT gate have been fabricated using a Nb/AlO/sub x//Nb Josephson-junction technology and tested. A fan-in operation of the phase-distributing branch and the first full operation of the INHIBIT gate are successfully demonstrated. As an example of the EPL logic circuits consisting of plural gates on a single ground reference, a simulation of a 2-bit full adder circuit is also presented. >

A Josephson four-bit full adder using direct coupled functional gates

A Josephson 4-bit full adder circuit using functional direct coupled gates has been designed and studied through computer simulations. The circuit consists of only 27 gates taken from a complete logic family composed of OR, AND, EXOR and MAJORITY gates. The proposed adder scheme needs 180 Josephson junctions and 150 thin film resistors. The computed critical path delay was found 180 ps/4bits for carry propagation, with a power dissipation estimated to be less than 100 μW on the basis of a Nb/Pb-In technology with 4 μm minimum linewidth and with a Josephson current density of 1000 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The worst case total add time for the 4 bits has been found less than 300 ps.

A flow-mode, self-steering, cellular multiplier-summation processor

Flow-mode or stream-processing digital systems have been proposed in which code, control and data are constantly moving so that multiple instructions are processed concurrently. We show the design of a flow-mode cellular array processor which can perform a number of two's complement fixed-point arithmetic operations. These operations are: three operand addition and/or subtraction, two operand multiplication and vector inner-product. Operand sizes are: 2N bit for addition and subtraction operands, andN bit for multiplication operands. Results are 2N bit. The network can simultaneously operate on 4N+2 datasets with any mix of the above operations being handled. The processor is based on the use of asynchronous cellular arrays. Given a continued flow of input datasets, the effective computation time is worst-case propagation time within one cell. A typical cell contains a 1-bit position 3-input full adder with associated input data storage. Thus the effective computation time is independent of the operand bit length.