Implementation Topology of Full Adder Cells

Abstract

Abstract Design of different complementary metal-oxide-semiconductor (CMOS) topologies of 1-bit full adder (FA) cell in terms of power, delay, power-delay-product (PDP) and energy-delay-product (EDP) have been analyzed for the application of the intelligent systems. The FA cells have been implemented with respect to the different CMOS topologies such as complementary-CMOS (C-CMOS), complementary pass-transistor logic (CPL), CMOS transmission gates (TGA), and CMOS transmission function (TFA) and simulated at 180 nm technology. The work has been extended to the comparison of FA cell implementation using the increasingly demanding ultra-thin-body silicon-on-insulator (UTBSOI) transistors. Based on the simulation results, the application of UTBSOI in the FA cell has resulted in 26.7%, 24.3%, 44.6% and 44.7% improvements over that of best design architecture reported in this literature in terms of power, delay, PDP, and EDP, respectively.