A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

Candy Goyal,Jagpal Singh Ubhi,Balwinder Raj

doi:10.1155/2018/3501041

Abstract

In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achieve reduction in leakage power and GBN up to 60% and 80%, respectively, as compared to the best reported approximate FA circuits. The modified approximate FA also achieves 83% reduction in leakage power as compared to conventional FA. Finally, application level metrics such as peak signal to noise ratio (PSNR) are considered to measure the performance of all the proposed approximate FAs.

Highlights

In today’s electronic driven epoch, demand of high speed electronic devices has put tremendous pressure on VLSI designers to develop low leakage and high speed arithmetic circuits
The results are discussed with respect to the average power, delay, power delay product (PDP), leakage power, and ground bounce noise (GBN) performance metrics
This paper presented four modified approximate adders which minimize the leakage power as well as controlling the GBN in transition mode

Summary

Introduction

In today’s electronic driven epoch, demand of high speed electronic devices has put tremendous pressure on VLSI designers to develop low leakage and high speed arithmetic circuits. A sleep circuit with three NMOS transistors and one PMOS transistor is presented [9], which reduces leakage power and GBN but requires large silicon area. This technique has large propagation delay and it requires two separate control signals, which further increases complexity Another circuit of power gating with stacking [11] is presented to reduce the leakage power and GBN in 10T FA circuit. This technique has penalty of increase in delay and area due to extra transistors. Average power dissipation and number of transistors are reduced at the expense of accuracy in conventional adder, but they consume large leakage power Another inexact FA [20] is presented which used 10 transistors for one-bit FA. We have modified the approximate adders with proposed sleep circuit to reduce leakage power and GBN

Proposed Circuit

Simulation Setup

Results and Discussion

Conclusion