A novel technique for static leakage reduction in 16 nm CMOS design

Abstract

ABSTRACTA novel technique for static leakage reduction in CMOS technology is proposed in this paper. This technique uses high and low values of threshold voltage as well as high and low values of gate oxide width in the design. Hence, the proposed technique is named as Dual Threshold and dual Oxide for Static power reduction (DTOS). Simulation results have been carried out in a 3-input nand gate and 1-bit conventional full adder circuits using 16 nm CMOS technology. Comparison of the proposed technique, i.e. DTOS is done with some of the existing techniques of leakage reduction like multi-threshold CMOS (MTCMOS), dual-Vth and dual-Tox. The DTOS technique reduces an average of 75.4% of static power consumption as compared with MTCMOS, dual-Vth and dual-Tox approaches for leakage reduction for a 3-input nand gate. For a 1-bit full adder circuit, the novel technique reduces an average of 69.1% of the static power as compared to the above-mentioned techniques of power reduction. The delay of the proposed technique is increased with respect to MTCMOS technique whereas it is improved in other cases.