Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics

Xingyuan Tong,Tiantian Sun

doi:10.1155/2016/6029254

Xingyuan Tong, Tiantian Sun

Open Access

https://doi.org/10.1155/2016/6029254

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Abstract

Low-power analog-to-digital converter (ADC) is a crucial part of wearable or implantable bioelectronics. In order to reduce the power of successive-approximation-register (SAR) ADC, an improved energy-efficient capacitor switching scheme of SAR ADC is proposed for implantable bioelectronic applications. With sequence initialization, novel logic control, and capacitive subconversion, 97.6% switching energy is reduced compared to the traditional structure. Moreover, thanks to the top-plate sampling and capacitive subconversion, 87% input-capacitance reduction can be achieved over the conventional structure. A 10-bit SAR ADC with this proposed switching scheme is realized in 65 nm CMOS. With 1.514 KHz differential sinusoidal input signals sampled at 50 KS/s, the ADC achieves an SNDR of 61.4 dB and only consumes power of 450 nW. The area of this SAR ADC IP core is only 136 μm × 176 μm, making it also area-efficient and very suitable for biomedical electronics application.

Highlights

With the feature size of integrated circuits downscaled to nanoscale, the integration level of System-on-Chip (SoC: System-on-Chip) has been increased dramatically
For some special applications, such as battery-powered or wirelesspowered implantable bioelectronics, low-power consumption and miniaturized size have become the key factors of the system
To verify the applicability of this proposed scheme, a 10-bit 50 KS/s SAR analog-to-digital converter (ADC) that can be used in multichannel neural recording implant is realized in 65 nm CMOS

Summary

Introduction

With the feature size of integrated circuits downscaled to nanoscale, the integration level of System-on-Chip (SoC: System-on-Chip) has been increased dramatically. An improved energy-efficient capacitor switching procedure for charge scaling SAR ADC is proposed. For power-efficiency, area reduction, and easy realization in CMOS process, two 1-bit capacitor arrays are combined to generate the last 2 bits. This innovation comes from the attenuation capacitor based dual-array charge scaling structure [7], in which the attenuation capacitor would be an integral multiple of unit capacitor, 2C, only when the LSB array just converts 1 bit [8]. To verify the applicability of this proposed scheme, a 10-bit 50 KS/s SAR ADC that can be used in multichannel neural recording implant is realized in 65 nm CMOS.

Proposed Switching Procedure

Switching Energy Analysis

Findings

Conclusion