A Study on Coarse Stage Bit Allocation to Improve Power Efficiency of a 10-bit Coarse-Fine SAR ADC Implemented in 65nm CMOS Process for Environmental Sensing Applications

Abstract

Energy consumption is very critical for environmental monitoring using wireless sensor networks, thus, every block must be designed to consume low energy to be within the limited energy budget of a sensor node. In the context of improving the power efficiency of the analog-to-digital converter (ADC), for this specific application, successive approximation register (SAR) ADC is the best architecture to use. In addition, coarse-fine technique has been proven to reduce power consumption in SAR ADCs. However, design considerations involving the coarse ADC bit allocation are important but not discussed in literature. These includes the following: trade off between resolution of the coarse stage and the accuracy of the ADC; trade off between the energy consumption, accuracy and speed of the comparator block; and trade off between energy consumption and accuracy of different switching schemes for the digital-to-analog (DAC) block. This project produced models of these trade-offs, provided a methodology in designing coarse-fine SAR ADCs, implemented two ADCs in the schematic level: the one with the lowest energy consumption; and the one with the highest Schreier figure of merit (FoMs), and implemented the ADC with the lowest energy consumption in the layout level. Optimization using the MATLAB model in the DAC lead to k = 4 which gives the lowest power and k = 3 which gives the highest Schreier FoM. Schematic implementation at 50kSps of k = 4 and k = 3 gave: 2.201pJ and 2.3617pJ switching energy; 9.2 and 9.3 ENOB; and 170.96 dB and 170.72 dB Schreier FoM, respectively. This project was also able to match the trends of the models to the simulations although there are deviations of values. However, ENOBs fall within the target range of ENOBs.