A low-power hybrid ADC architecture for high-speed medium-resolution applications

Abstract

A low-power hybrid analog-to-digital converter (ADC) architecture for high-speed medium-resolution applications is introduced. The architecture is a subranging time-interleaved ADC. In the first stage, a fast flash ADC resolves the three most significant bits. The remaining bits are generated by four time-interleaved low-power successive approximation register (SAR) ADCs, leading to 8-bit 1GS/s operation overall. A combined sample-and-hold and capacitive digital-to-analog converter (SHDAC) circuit is proposed to perform front-end sampling and to shift the sampled voltage to the optimal operating region of the second stage. A buffer stage suppresses the loading effects and kickback noise of the SAR ADC on the SHDAC in each channel. Each SAR ADC is implemented with a comparator-based asynchronous binary-search (CABS) architecture. A switching scheme in the voltage buffer stage relaxes the amplifier specification requirements, leading to significant power reduction. The hybrid ADC was designed and simulated with a mix of behavioral models and transistor-level circuit designs in 130nm CMOS technology. It has a signal-to-noise-and-distortion ratio (SNDR) of 47.5dB with an input signal close to the Nyquist frequency. The estimated power consumption is 17mW from a 1.2V supply.