An efficient-energy switching scheme with 99.57% reduction in switching energy for SAR ADC

Abstract

An efficient-energy switching scheme for a successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed switching scheme combines a new switching method and the spilt capacitor technique. The new switching method consumes no energy in the first three comparison cycles and introduces negative energy (Tong and Zhang in Electron Lett 51(14):1052–1054, 2015; Osipov and Paul in Two advanced energy-back SAR ADC architectures with 99.21 and 99.37% reduction in switching energy, Kluwer Academic Publishers, Dordrecht, 2016) in the following comparisons. The proposed switching scheme achieves 99.57% less switching energy and 75% less area over the conventional architecture, besides the proposed switching scheme achieves high linearity at the same time which DNL is just 0.119 LSB, INL is 0.119LSB.