Energy-efficient switching scheme for SAR ADCs using two reference levels

Abstract

A highly energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The proposed switching scheme needs only two reference levels by using the merge-and-split technique, which eliminates the need of the extra reference voltage (Vcm). The switching procedure is performed on the simple binary weighted capacitor arrays without any capacitor-splitting. Compared with the conventional scheme, the proposed switching scheme can achieve 98.45% saving in switching energy and 75% capacitors-area reduction. Besides, because two capacitor arrays are switched symmetrically, the common-mode voltage of capacitive digital-to-analog converter (CDAC) keeps constant until the LSB cycle. The proposed switching scheme is verified in a 0.6-V 10-bit 200-kS/s SAR ADC in 40 nm CMOS technology.