Xilinx Virtex-5 Field Programmable Gate Research Articles

RDCSAE-RKRVFLN: A unified deep learning framework for robust and accurate DOA estimation

This paper introduces an innovative unified deep learning (DL) model, “reduced deep convolutional stack autoencoder (RDCSAE)-robust kernel-based random vector functional link network (RKRVFLN)” (RDCSAE-RKRVFLN), for addressing practical challenges like phase and gain uncertainty, mutual coupling effects, and element position errors in direction of arrival (DOA) estimation. The RDCSAE utilizes deep convolutional neural network (DCNN) and stack autoencoder (SAE) for robust feature extraction. The RKRVFLN integrates a concise SAE output with kernel-based learning. Thus, the integration of RDCSAE (suitable for unsupervised feature extraction) and RKRVFLN (for supervised learning) in the developed model results in efficient use of limited training data. Performance metrics of this method include among others the accuracy (separation between sources), root mean square error (RMSE), signal-to-noise ratio (SNR), etc. The method performs better than existing data driven methods in terms of computational efficiency, faster learning speed, enhanced model generalization, higher accuracy, and shorter event regression time and empirical methods. In the presence of above mentioned four perturbations, this method successfully resolves multiple sources with a resolution of 0.3° with a RMSE of 0.00376. For real time application, the paper implements RDCSAE-RKRVFLN on a high-speed reconfigurable Xilinx Virtex-5 field-programmable gate array (FPGA) realizing a digital DOA estimator for one source. The hardware estimates the DOA with a maximum error of 0.01953125 which follows closely the simulation results indicating the efficiency and feasibility of the method.

Resource-aware Montgomery modular multiplication optimization for digital signal processing

Homomorphic encryption is an important technology for protecting data privacy, and the performance of modular multiplication directly affects the efficiency of homomorphic encryption. Currently, there are numerous FPGA-based acceleration techniques targeting modular multiplication. However, many of these implementations require substantial hardware resources or suffer from resource imbalance. This leads to a lower throughput. Therefore, we present a novel FPGA-based implementation of Montgomery Modular Multiplication aimed at addressing these challenges. Our design employs a suitable radix bit width and word size based on the digital signal processing (DSP) bit width rather than the conventional binary powers of two. We aim to instantiate more modular multipliers using limited resources while minimizing latency. We also introduce a novel DSP cascade structure, called parallel grouping cascade DSP, which reduces the number of clock cycles of internal multipliers. To balance the ratio of lookup table (LUT) and DSP usage, we also use multipliers implemented in the LUT to replace some DSPs. Our results, implemented on Xilinx Virtex-7 field-programmable gate array (FPGA), demonstrate more than 27% improvement in throughput on 1024-bit modular multiplication and more than 70% improvement on 2048-bit compared to the best previous state-of-the-art references.

A Flexible Hardware Accelerator for Booth Polynomial Multiplier

This article presents a parameterized/flexible hardware accelerator design tailored for the Booth polynomial multiplication method. The flexibility is achieved by allowing users to compute multiplication operations across various operand lengths, reaching up to 212 or 4096 bits. Our optimization strategy involves resource reuse, effectively minimizing the overall area cost of the Booth accelerator design. A comprehensive evaluation compares the proposed multiplier design with several non-digitized bit-serial polynomial multiplication accelerators. Implementation is realized in Verilog HDL using the Vivado IDE tool, featuring diverse operand sizes, and post-place and route assessments are performed on the Xilinx Virtex-7 field-programmable gate array device. For the largest considered operand size of 1024 × 1024, our Booth accelerator utilizes 1434 slices and can operate on a maximum frequency of 523.56 MHz. A single polynomial multiplication operation requires 0.977 μs and the total power consumption is 927 mW. Moreover, a comparison to state-of-the-art accelerators reveals that the proposed flexible accelerator is 1.34× faster in computation time and 1.05× more area-efficient than the recent dedicated polynomial multiplication design. Therefore, the implementation results and comparison to the state of the art show that the proposed accelerator is suitable for a wide range of cryptographic applications.

A novel digital intermediate frequency module for hyperspectral microwave radiometers based on the parallel fast Fourier transform algorithm.

Microwave radiometers, possessing all-day and all-weather operational capabilities, are extensively utilized in the exploration of planetary atmospheres and surfaces. The potential of the hyperspectral detection technology to enhance the precision and resolution of microwave radiometer detection has made it a crucial research focus. This paper introduces an intermediate frequency (IF) module for hyperspectral microwave radiometers. The IF module is constructed with two 6.4 gigabit samples per second sampling-rate analog-to-digital converter (ADC) chips and a Xilinx Virtex-7 field programmable gate array. By implementing a parallel fast Fourier transform algorithm and a pipeline architecture, the IF module can efficiently process all ADC sampling data in real-time, generating 512 channels of output for each ADC. The test results, including linearity, sensitivity, and flatness, are presented and thoroughly analyzed for the IF module. Furthermore, the module is interfaced with the radio frequency front-end of the microwave radiometer to measure hot and cold calibration sources and assess its sensitivity. When combined with a suitable front-end receiver, the IF module can form a radiometer system suitable for various applications of microwave remote sensing.

An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields

This article proposes a flexible hardware accelerator optimized from a throughput and area point of view for the computationally intensive part of elliptic curve cryptography. The target binary fields, defined by the National Institute of Standards and Technology, are GF(2163), GF(2233), GF(2283), GF(2409), and GF(2571). For the optimization of throughput, the proposed accelerator employs a digit-parallel multiplier. The size of the digit is 41 bits. The proposed accelerator has reused the multiplication and squaring circuit for area optimization to compute modular inversions. Flexibility is included using three additional buffers on top of the proposed accelerator architecture to load different input parameters. Finally, a dedicated controller is used to optimize control signal handling. The architecture is modeled using Verilog and implemented up to the post-place-and-route level on a Xilinx Virtex-7 field-programmable gate array. The area utilization of our accelerator in slices is 1479, 1998, 2573, 3271, and 4469 for m=163 to 571. The time needed to perform one-point multiplication is 7.15, 10.60, 13.26, 20.96, and 30.42 μs. Similarly, the throughput over area figures for the same key lengths are 94.56, 47.21, 29.30, 14.58, and 7.35. Consequently, achieved results and a comprehensive performance comparison show the suitability of the proposed design for constrained environments that demand throughput/area-efficient implementations.

A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication

The ring learning with error (RLWE)-based fully homomorphic encryption (FHE) scheme has become one of the most promising FHE schemes. However, its performance is limited by the homomorphic multiplication, especially the polynomial multiplication which occupies major computing resources. Therefore, efficient implementation of polynomial multiplication is crucial for high-performance FHE applications. In this article, we present an area-efficient and highly unified reconfigurable multicore number theoretic transform (NTT)/inverse NTT (INTT) architecture (named MCNA), which employs NTT and INTT for polynomial multiplier with a variable number of reconfigurable processing elements. To reduce latency, MCNA merges the preprocessing and postprocessing into the constant-geometry NTT and INTT, respectively. Also, a reconfigurable modular multiplier based on digital signal processor (DSP) is proposed to speed up the modular multiplication. In order to avoid designing independent memory access pattern for INTT, a unified read/write structure of NTT/INTT is presented. Furthermore, a novel memory access pattern named “cyclic-sharing” is proposed to reduce 25% memory capacity. MCNA is evaluated on a Xilinx Virtex-7 field-programmable gate array (FPGA) platform. Running at 250-MHz clock frequency, the throughput of MCNA for NTT/INTT achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.78\times \sim 9.32\times $ </tex-math></inline-formula> improvements in comparison to prior works, while the area efficiency of lookup table (LUT) and flip-flop (FF) is improved by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.25\times \sim 4.79\times $ </tex-math></inline-formula> . For polynomial multiplication, the throughput of MCNA achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.73\times \sim 7.69\times $ </tex-math></inline-formula> enhancements, as well as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.13\times \sim 14.8\times $ </tex-math></inline-formula> area efficiency improvements.

A digital direction of arrival estimator based on fast on-line sequential random vector functional link network

This article develops a fast online sequential random vector functional network. In this network, input nodes are connected to both hidden nodes and output nodes. This architecture results in high-speed learning and testing. The network estimates the direction of arrival from signals received by the sparse array in real-time. Neither noisy signal nor effect of mutual coupling among array elements affect the estimation appreciably using the network. The network shows competitive performance in terms of learning speed, accuracy, short event regression time, simplicity, and robustness in comparison to other state-of-the-art methods such as support vector regression, extreme learning machine, and online sequential extreme learning machine. Finally, validation of the network translation into a hardware platform using a fast digital high-speed reconfigurable Xilinx Virtex-5 field-programmable gate array embedded processor for single-source detection completes the work. Comparison with reported measurement shows results with good accuracy and low root mean square error both by the network and its hardware-implemented platform. The direction of arrival estimation is thus possible using the network either through a computer or dedicated hardware as per necessity.

High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems.

Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead.

ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture

In this article, we propose a novel data detection algorithm and a corresponding VLSI design for massive multiuser (MU) multiple-input-multiple-output (MIMO) wireless systems. Our algorithm uses alternating direction method of multipliers (ADMM)-based infinity-norm-constrained equalization and is called ADMIN. ADMIN is an iterative algorithm that outperforms linear detectors by a large margin when the ratio between the numbers of base-station (BS) and user antennas is small. In the first iteration, ADMIN computes the linear minimum mean-square error (MMSE) solution, which is sufficient when the ratio between the numbers of BS and user antennas is large. We develop time-shared and iterative VLSI architectures for LDL-decomposition-based soft-output ADMIN supporting 16- and 32-user systems. We present application-specific integrated circuit (ASIC) designs for 16-64 antenna base stations in 28-nm CMOS that supports up to 64 quadrature amplitude modulation (QAM). The 16-user ADMIN ASIC achieves 303 Mb/s while dissipating 85 mW. The 32-user ADMIN ASIC achieves 287 and 241 Mb/s while dissipating 121 and 135 mW for 32 and 64 BS antennas, respectively. ADMIN has also been implemented on a Xilinx Virtex-7 field-programmable gate array (FPGA) and is compared with state-of-the-art massive MIMO data detectors.

High performance IIR filter implementation on FPGA

This paper presents an improved design of reconfigurable infinite impulse response (IIR) filter that can be widely used in real-time applications. The proposed IIR design is realized by parallel–pipeline-based finite impulse response (FIR) filter. The FIR filters have excellent characteristics such as high stability, linear phase response and fewer finite precision errors. Hence, FIR-based IIR design is more attractive and selective in signal processing. In addition, the other two modern techniques such as look-ahead and two-level pipeline IIR filter designs are also discussed. All the said designs have been described in hardware description language and tested on Xilinx Virtex-5 field programmable gate array board. The implementation results show that the proposed FIR-based IIR design yields better performance in terms of hardware utilization, higher operating speed and lower power consumption compared to conventional IIR filter.

FPGA-Based Deep Convolutional Neural Network of Process Adaptive VMD Data With Online Sequential RVFLN for Power Quality Events Recognition

In this article, self-adaptive variational mode decomposition (SAVMD), deep convolutional neural networks (DCNN), and online-sequential random vector functional link networks (OSRVFLN) are integrated to categorize the single as well as combined power quality events (PQEs) in real time. The SAVMD method is proposed to optimize both the number of decomposition and data-fidelity factor to extract the most efficient band-limited mode (BLM) based on entropy and Kurtosis index. The most discriminative unsupervised features are extracted automatically using a DCNN from the BLM of SAVMD. The extracted distinct feature vector is fed to the proposed supervised OSRVFLN classifier to train accurately by minimizing the training cross-entropy loss with an increment in the number of hidden nodes for obtaining the maximum classification accuracy of the complex PQE patterns in noisy and noise-free environments. The automatic efficacious feature extraction, superior classification accuracy, noise immunity, and short event detection time are the major advantages of the proposed SAVMD-DCNN-OSRVFLN method. Finally, the novel methodology is implemented in a fast digital Xilinx Virtex-5 field-programmable gate array embedded processor to validate the practicability and feasibility of the proposed method in real-time.

PUF-Based Secure Chaotic Random Number Generator Design Methodology

Pseudorandom number generators (PRNGs) play a pivotal role in generating key sequences of cryptographic protocols. Among different schemes, a simple chaotic PRNG (CPRNG) exhibits the property of being extremely sensitive to the initial seed and, hence, unpredictable. However, CPRNG is vulnerable if the initial seed is compromised. In this brief, we propose a novel physical unclonable function-based CPRNG (PUF-CPRNG), where the initial seed is secured by generating it from PUF. Furthermore, the proposed PUF-CPRNG includes dynamic refreshing logic to ensure that the random numbers generated are nonperiodic. To further secure the PUF-CPRNG, the feedback values of CPRNG are fed from PUF. An hardware architecture for the proposed methodology has been designed, and the proof of concept implementation was carried out using Xilinx Virtex-7 field-programmable gate array (FPGA). The proposed PUF-CPRNG passes the statistical test NIST 800-22, ENT, and correlation analysis.

A signed pulse-train-based image processor-array for parallel kernel convolution in vision sensors

PurposeThe purpose of this paper is to design a kernel convolution processor. High-speed image processing is a challenging task for real-time applications such as product quality control of manufacturing lines. Smart image sensors use an array of in-pixel processors to facilitate high-speed real-time image processing. These sensors are usually used to perform the initial low-level bulk image filtering and enhancement.Design/methodology/approachIn this paper, using pulse-width modulated signals and regular nearest neighbor interconnections, a convolution image processor is presented. The presented processor is not only capable of processing arbitrary size kernels but also the kernel coefficients can be any arbitrary positive or negative floating number.FindingsThe performance of the proposed architecture is evaluated on a Xilinx Virtex-7 field programmable gate array platform. The peak signal-to-noise ratio metric is used to measure the computation error for different images, filters and illuminations. Finally, the power consumption of the circuit in different operating conditions is presented.Originality/valueThe presented processor array can be used for high-speed kernel convolution image processing tasks including arbitrary size edge detection and sharpening functions, which require negative and fractional kernel values.

Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W 32 , W 64 , and W 128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

Algorithm and VLSI Design for 1-Bit Data Detection in Massive MIMO-OFDM

The use of low-resolution data converters in the radio-frequency (RF) chains of all-digital massive multiple-input multiple-output (MIMO) basestations promises significant reductions in power consumption, hardware costs, and interconnect bandwidth. We propose a quantization-aware data-detection algorithm which mitigates the performance loss of 1-bit quantized massive MIMO orthogonal frequency-division multiplexing (OFDM) systems. Since the system performance heavily depends on the quality of channel estimates, we also develop a nonlinear 1-bit channel estimation algorithm that builds upon the proposed data detection algorithm. We show that the proposed algorithms significantly outperform linear data detectors and channel estimators in terms of bit error rate. For the proposed nonlinear data detection algorithm, we develop a very large scale integration (VLSI) architecture and present implementation results on a Xilinx Virtex-7 field programmable gate array (FPGA). Our implementation results are, to the best of our knowledge, the first for 1-bit massive MU-MIMO-OFDM systems and demonstrate comparable hardware efficiency with respect to state-of-the-art linear data detectors designed for systems with high-resolution data converters, while achieving lower bit error rate.

Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography

In this paper, an area-time efficient hardware implementation of modular multiplication over five National Institute of Standard and Technology (NIST)-recommended prime fields is proposed for lightweight elliptic curve cryptography (ECC). A modified radix-2 interleaved algorithm is proposed to reduce the time complexity of conventional interleaved modular multiplication. The proposed multiplication algorithm is designed in hardware and separately implemented on Xilinx Virtex-7, Virtex-6, Virtex-5, and Virtex-4 field-programmable gate array (FPGA) platforms. On the Virtex-7 FPGA, the proposed design occupies only 1151, 1409, 1491, 2355, and 2496 look up tables (LUTs) and performs single modular multiplication in 0.93 μs, 1.18 μs, 1.45 μs, 2.80 μs, and 4.69 μs with maximum clock frequencies of 207.1 MHz, 190.7 MHz, 177.3 MHz, 137.6 MHz, and 111.2 MHz over five NIST prime fields of size 192, 224, 256, 384, and 521 bits, respectively. The hardware implementations on the Virtex-6, Virtex-5, and Virtex-4 FPGAs also show that the proposed design is highly efficient in terms of hardware resource utilization and area-delay product compared with other designs for modular multiplication.

High Speed Partial Pattern Classification System Using a CAM-Based LBP Histogram on FPGA

This letter proposes a novel partial pattern classification system that uses local binary patterns as a classifier and a content-addressable memory, which has the parallel search capability, to perform classification at a higher speed. The proposed pattern classification system uses Manhattan distance for class assignment and further uses logical resources on the Xilinx Virtex-7 field-programmable gate array to perform classification. Our proposed system assigns a class to a pattern of any size and shape in as less as $1.12~\mu \text{s}$ , which is 33% faster than the state-of-the-art pattern classification system.

Efficient Design and Implementation of Energy Detection-Based Spectrum Sensing

Cognitive radio allows opportunistic spectrum access by finding and using temporally and spatially unused radio channels to enhance the utilization of scarce radio spectrum. Various spectrum sensing techniques have been proposed to detect the availability of unoccupied radio channels. In this article, we first briefly discuss the merits of various spectrum sensing techniques. We then present an efficient hardware architecture for energy detection-based spectrum sensing. We discuss various design parameters and features, such as transform length, window selection, window overlap, ensemble averaging, and dynamic thresholding for efficient realization of the designed spectrum sensing module. Then, an efficient hardware architecture for an optimal energy detection-based spectral estimator is presented. To reduce the computational complexity, we utilize a polyphase filter structure. For the high-performance implementation of the proposed spectrum sensing architecture, we use cutset retiming, and for the compact realization, we use the time-multiplexing technique to reuse hardware resources. We model our spectrum sensing module in both floating-point and fixed-point representations using our custom-developed library of numerical operations. The synthesizable parameteric model of the energy detection-based spectrum sensing module is developed in Verilog hardware description language. The architecture of the designed spectrum sensing module is implemented on a Xilinx Virtex-7 field-programmable gate array and operates at 327 MHz. The cycle-accurate bit-true hardware simulation results are verified against its fixed-point software simulation results. An ASIC architecture of the designed spectrum sensing module is estimated to occupy \(5.65\,\hbox {mm}^2\) and dissipate 9.10 mW from a 1.05-V supply while operating at 200 MHz in a standard 32-nm CMOS technology for a 200 MHz bandwidth.

New Hardware Architecture for Self-Organizing Map Used for Color Vector Quantization

In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. [Formula: see text] SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.

Efficient Hardware Implementation of Modular Arithmetic and Group Operation Over Prime Field

The need for secure communication over the network has increased drastically over recent years, and Elliptic Curve Cryptography (ECC) carries out a significant role in moving secured information. In this work, a hardware implementation of modular arithmetic and group operations over the prime field for an Elliptic Curve Cryptography Processor (ECP) for an efficient security system is proposed. The modular addition or subtraction operation takes only one clock cycle and the modular multiplication, which is designed using the interleaved modular multiplication method, requires 257 clock cycles. For elliptic curve group operation separate point doubling (PD) and point addition (PA) architectures are implemented in Jacobean coordinates. These new architectures are simulated in a Xilinx ISE 14.7. After that, the architectures are implemented in Xilinx Virtex-7 field-programmable gate array (FPGA) with the VHDL language. Proposed modular arithmetic and group operations can be utilized to design an Elliptic Curve Point Multiplication (ECPM).