High performance IIR filter implementation on FPGA

Debarshi Datta,Himadri Sekhar Dutta

doi:10.1186/s43067-020-00025-4

Abstract

This paper presents an improved design of reconfigurable infinite impulse response (IIR) filter that can be widely used in real-time applications. The proposed IIR design is realized by parallel–pipeline-based finite impulse response (FIR) filter. The FIR filters have excellent characteristics such as high stability, linear phase response and fewer finite precision errors. Hence, FIR-based IIR design is more attractive and selective in signal processing. In addition, the other two modern techniques such as look-ahead and two-level pipeline IIR filter designs are also discussed. All the said designs have been described in hardware description language and tested on Xilinx Virtex-5 field programmable gate array board. The implementation results show that the proposed FIR-based IIR design yields better performance in terms of hardware utilization, higher operating speed and lower power consumption compared to conventional IIR filter.

Highlights

The basic function of a filter is to remove unwanted portion of a given signal or suppress noise and to excerpt suitable parts of that signal for further processing [1]
This paper specially focused on the Discrete Fourier Transform (DFT) filter banks which are implemented by infinite impulse response (IIR) filters instead of finite impulse response (FIR) filters
This paper focuses on design and implementation of IIR filters on field programmable gate array (FPGA) device

Summary

Introduction

The basic function of a filter is to remove unwanted portion of a given signal or suppress noise and to excerpt suitable parts of that signal for further processing [1]. The proposed FIR-based IIR design allows to reduce computation time and to optimize the available hardware resources in the FPGA platform. For implementation of an Nth order IIR digital filter, architecture requires (2N + 1) number of coefficients, (2N + 1) number of multipliers, (2N) number of two-input adders and N number of registers.

Results

Conclusion