Work Function Of Gate Electrode Research Articles

Gate Electrode Work Function Engineered Nanowire FET with High Performance and Improved Process Sensitivity

MOSFETs have been used in integrated circuits for a long time. These were replaced by FinFET’s in 2011. But for short-channel devices, FinFET’s have low performance due to various effects like velocity saturation, hot carrier effect, drain-induced barrier lowering, channel length modulation, fringing field effect, sub-threshold conduction, threshold voltage roll-off, etc. Gate All Around FET (GAA FET) is the best device that will replace the FinFET’s. Therefore, during the fabrication process, it is crucial to investigate the effects of process variations caused by changes in device dimensions. This research discusses the performance of the proposed device due to process variations. The effect of changes in radius, gate oxide thickness, gate length, and channel doping on GAA FET has been discussed in detail.

Design and implementation of the logic gates using electrically doped configurable polarity control double gate tunnel FET

This paper designs and implements the basic logic and universal gates based on the proposed electrically doped, configurable polarity control double gate tunnel FET (ED-CPC-DGTFET). In contrast to the CMOS and MOSFET, the primary concern of the proposed device is to overcome the transistor count needed to design logic gates. A few compact realizations of logic gates have been reported earlier using conventional double-gate TFETs. The main key to designing and implementing logic gates with the proposed structure is controlling the channel’s tunneling barrier height by altering the gate electrode work function. Additionally, abrupt interband tunneling of TFET by varying gate bias makes the device appropriate for implementing logic gates. The proposed device has a dynamic configuration that can change from n-type to p-type DGTFET by varying the bias at PG-1 and PG-2. Since lightly doped TFETs have a low ON-state current therefore, a high-k material (HfO 2 ) is employed in place of SiO 2 on top of the source side to enhance the ON-state current. Using two-dimensional simulations, the device is designed to implement logic gates with gate lengths of 50 nm and silicon body thicknesses of 10 nm (t si ). OR and AND logic gates are implemented using the n-type ED-CPC-DGTFET structure, and universal gates are implemented using the p-type variant of the proposed ED-CPC-DGTFET structure by independently biasing the top and bottom gates against various inputs.

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

AbstractIn the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance.

Analysis and Design of MBCFET and Their Circuit Application in Current Mirror and DRAM

This research paper addresses the challenges associated with transistor downscaling, particularly short channel effects (SCEs) in conventional silicon metal-oxide-semiconductor field-effect transistors (Si MOSFETs), and introduces Multi-Bridge-Channel MOSFETs (MBCFETs) as a potential solution. This study explores their attributes, emphasizing flexibility and faster switching, and comprehensively examines device parameters, fabrication processes, and simulation frameworks, offering a detailed analysis of critical factors influencing MBCFET performance. Investigating the intricate relationship between nanosheet dimensions and device characteristics, the research provides insights for optimized design and integration into future semiconductor technologies. The research looks at how the gate electrode's work function, the nanosheets' thickness and count, and the different types of doping affect important device properties such as transconductance, drive current, OFF-state current, and threshold voltage. Furthermore, the study is being carried out to form a current mirror and DRAM circuit by using the proposed MBCFET. This study demonstrates the transformative potential of MBCFETs in high-performance electronic applications.

Experimental circuit design and TCAD analysis of ion sensitive field effect transistor (ISFET) for pH sensing

In this work, we have investigated, both theoretically and experimentally, the analog study of the ion-sensitive field effect transistor (ISFET) and the circuit design for pH sensing. The gate electrode work function engineered on ISFET has been rigorously investigated for the analog/RF applications by using the Cogenda Visual TCAD tool. Based on its I–V characteristics, we may deduce that molybdenum, with a work function of 4.75 eV, has a larger threshold voltage, switching ratio (104) and lower leakage current (10−3) than aluminum at 300 K. In addition, we experimentally investigated the enhancement in pH sensing. ISFET display instability, often referred to as drift, in the form of a gradual, monotonic, temporal increase in the device’s threshold voltage. The validation of the observations was done by increasing the value of the pH as follows: 4.67, 5.9, 7.5, 8.57, and 9.3 which was checked by pH meter.

Design and analysis of Z shaped InGa0.5As0.5/Si tunnel FET using non-equilibrium Green’s function model for hydrogen gas sensing application

—In this paper, a high-k stacked gate Z shaped hetero-juncture TFET (Z-HTFET) is introduced as transducer sensor for the application of hydrogen gas detection. The positioning of stacked gate over the entire source region resulting Z shaped TFET exhibits vertical line tunneling mechanism between the source and the channel yielding higher ON state current (Id) as compared to conventional double gate (DG) TFET. Further, the combination of low band gap source of In0.5Ga0.5As and hetero-gate dielectric engineering helps to facilitate improved device current, steeper subthreshold slope and lower leakage current (Ileak) conduction. Here, palladium (Pd) and the high-k gate stack (HfO2/SiO2) is used as the sensing platform. The induced shift in work function of Pd gate electrode due to the dissociation and diffusion of hydrogen gas molecules into the catalytic gate metal is considered as the detection metric for calculating the sensitivity of the proposed TFET based gas sensor. The behavior of the hydrogen gas sensor is studied using numerical device simulator in terms of surface potential, electric field, transfer characteristics, transconductance, Id/Ileak ratio with variation in work-function and finally Id/Ileak sensitivity is measured. The sensor behavior for a wide range of temperature is also examined to explore the temperature stability of the device. The comparative performance analysis of Z-HTFET with sensitivity of 95.26% establishes the superiority of the device for hydrogen gas sensing as compared to some of the recently reported FET based sensors.

Gate electrode work function engineered JAM-GS-GAA FinFET for analog/RF applications: Performance estimation and optimization

In this study, the gate electrode work function engineered Junctionless Accumulation Mode Gate Stack Gate All Around (JAM-GS-GAA) FinFET has been rigorously investigated for analog/RF applications. The simulated findings show that decreasing the gate electrode work function by 0.4 eV improves the static characteristics such as electric field (46.68%), electron mobility (55.0%), potential (5.74%), and electron concentration (2.97%). A 0.4 eV escalation in the gate electrode work function improves the analog parameters of the JAM-GS-GAA FinFET significantly in terms of leakage current (Ioff) (104 times), subthreshold swing (SS) (20.26%), switching ratio (Ion/Ioff) (102 to 106), and quality factor (QF) (25.54%), intrinsic gain (Av) (280.73%), early voltage (VEA) (62.12%), and output conductance (gd) (90.52%). The RF parameters follow the same trend as analog parameters. GFP and GTFP increased more than eight and ten times, respectively, with a surge in the gate electrode work function. Consequently, the findings of this research can assist engineers in designing nanoelectronic devices that meet their requirements.

Fully-Solution-Processed Enhancement-Mode Complementary Metal-Oxide-Semiconductor Carbon Nanotube Thin Film Transistors Based on BiI3 -Doped Crosslinked Poly(4-Vinylphenol) Dielectrics for Ultralow-Power Flexible Electronics.

The threshold voltage (Vth ) adjustment of complementary metal-oxide-semiconductor (CMOS) thin film transistors (TFTs) is one of the research hotspotsdue to its key role in energy consumption control of CMOS circuits. Here, ultralow-power flexible CMOS circuits based on well-matched enhancement-mode (E-mode) CMOS single-walled carbon nanotube (SWCNT) TFTs are successfully achieved through tuning the work function of gate electrodes, electron doping, and printing techniques. E-mode P-type CMOS SWCNT TFTs with the full-solution procedure are first obtained through decreasing the work function ofAg gate electrodes directly caused by the deposition of bismuth iodide(BiI3 )-doped solid-state electrolyte dielectrics. After synthetic optimization of dielectric compositions and semiconductor printing process, the flexible printed E-mode SWCNT TFTs show the high Ion /Ioff ratios of ≈106 , small subthreshold swing (SS) of 70-85mV dec-1 ,lowoperating voltages of ≈0.5 to -1.5V, good stabilityand excellent mechanical flexibility during 10000 bending cycles. E-mode N-type SWCNT TFTs are then selectively achieved via printing the polarity conversion ink (2-Amino-2-methyl-1-propanol (AMP) aselectron dopingagent) in P- type TFT channels. Last, printed SWCNT CMOS invertersare successfully constructed with full rail-to-rail output characteristics and the record unit static power consumption of 6.75 fW µm-1 at VDD of 0.2V.

Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

This study describes a single‐gate silicon on insulator junctionless metal–oxide–semiconductor field‐effect transistor (SJL‐MOSFET) with inserted buried 4H‐SiC p‐type layer (B‐SJL‐MOSFET). The embedded p‐type layer is placed at the bottom of the active regions, achieving the full depletion of the channel in the off‐state mode. The p‐type layer affects the depletion region of the channel, which helps us have a full depletion area with a lower gate electrode work function. The main reason for using SiC material instead of silicon is the higher electrostatic integrity and a shorter natural length than silicon, resulting in a better short channel effect (SCE). In addition, the high‐k oxide is stacked for achieving lower natural length and better subthreshold swing (SS). The p‐type layer improves the leakage current (Ioff) by ≈105 in the event that it slightly diminishes the on‐state current (Ion) and improves the SS. Improvement of off‐current is due to higher barriers between source‐channel side and reduces the parasitic BJT in the off‐mode.

Chemical modulation of conducting polymer gate electrode work function based double gate Mg2Si TFET for gas sensing applications

Chemical modulation of conducting polymer gate electrode work function based double gate Mg2Si TFET for gas sensing applications

Effect of Step Gate Work Function on InGaAs p-TFET for Low Power Switching Applications.

In this study, we theoretically investigated the effect of step gate work function on the InGaAs p-TFET device, which is formed by dual material gate (DMG). We analyzed the performance parameters of the device for low power digital and analog applications based on the gate work function difference (∆ϕS-D) of the source (ϕS) and drain (ϕD) side gate electrodes. In particular, the work function of the drain (ϕD) side gate electrodes was varied with respect to the high work function of the source side gate electrode (Pt, ϕS = 5.65 eV) to produce the step gate work function. It was found that the device performance varies with the variation of gate work function difference (∆ϕS-D) due to a change in the electric field distribution, which also changes the carrier (hole) distribution of the device. We achieved low subthreshold slope (SS) and off-state current (Ioff) of 30.89 mV/dec and 0.39 pA/µm, respectively, as well as low power dissipation, when the gate work function difference (∆ϕS-D = 1.02 eV) was high. Therefore, the device can be a potential candidate for the future low power digital applications. On the other hand, high transconductance (gm), high cut-off frequency (fT), and low output conductance (gd) of the device at low gate work function difference (∆ϕS-D = 0.61 eV) make it a viable candidate for the future low power analog applications.

Linearity and Analog Performance Analysis of Silicon Junctionless Bulk FinFET Considering Gate Electrode Workfunction Variability and Different Fin Aspect Ratio

Linearity and Analog Performance Analysis of Silicon Junctionless Bulk FinFET Considering Gate Electrode Workfunction Variability and Different Fin Aspect Ratio

Electrical Performance Enhanced Doping Less Tunnel Field Effect Transistor by Metal Electrode Work Function Engineering

Tunnel field effect transistor (TFET) has been proposed as one of the promising alternative devices to MOSFET since it has low power consumption and excellent subthreshold swing (SS) characteristics of less than 60 mV / dec. However, conventional TFET fabrication requires ion implantation process to form p-i-n structure in active region, which induces a random distribution of dopant atoms. In the nm-scale device, even a small number of dopant atom dispersion can cause electrical characteristic variations such as threshold voltage (Vt)1, so alternative method for forming p-i-n region instead of doping process is needed.Doping-less TFET (DL-TFET) introduces charge plasma concept2 that controls carrier concentration of Si region by band alignment in MOS contact not by doping process, so random dopant fluctuation (RDF) issue can be solved. Since the active region carrier concentration is determined by the work function of the metal electrode, it is necessary to analyze the device performance by the metal work function condition. In this work, we manufactured doping-less TFET with adapting various metal work function to enhance electrical performance, and conducted CV measurement in MOS structure to confirm Si band bending and charge plasma by analyzing flat band voltage (VFB).DL-TFET was fabricated on SOI wafer and the overall structure is shown in Fig. 1. (a). In the case of the source region, the metal work function must be larger than that of Si to form the p-type active area, and drain region, on the contrary, must have smaller work function for n-type active region. Obviously, gate electrode work function has similar work function to intrinsic Si. For fabricating DL-TFET, we conducted reactive ion etch (RIE) process to define Si active layer and formed gate oxide (SiO2) by thermal oxidation. Then, we deposited gate metal and removed source / drain region oxide for contact hole. Spacer oxide was deposited using PECVD to isolate each metal electrode, finally we deposited source / drain metal. IV characteristics are shown in Fig. 1. (b), (c) when Pt / W / Al is applied at source / gate / drain area and we compared IV curve of various metal electrode and thermal conditions.In addition, to confirm whether the charge plasma was formed as intended, we fabricated MOS capacitor with 10 nm oxide thickness as shown in Fig. 1. (d). Through frequency sweep, we determined suitable bias frequency and conducted CV measurement (see Fig. 1. (e), (f), (g)). Band bending and charge plasma were confirmed by evaluating VFB shift depending on work function of each MOS gate material (see Fig. 1. (h)). Finally, we discussed the optimal metal electrode combination in terms of ambipolar current, off current, on current and SS. Key Words: Charge plasma, Doping-less TFET, Work function, CV measurement References Changho Shin, Jeong-Kyu Kim, Gwang-Sik Kim, Hyunjae Lee, Changhwan Shin, Jong-Kook Kim, Byung Jin Cho, and Hyun-Yong Yu, “Random Dopant Fluctuation-Induced Threshold Voltage Variation-Immune Ge FinFET With Metal–Interlayer–Semiconductor Source/Drain,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 63, No. 11, pp 4167-4172, Nov 2016. doi: 10.1109/TED.2016.2606511 Raymond J. E. Hueting, Bijoy Rajasekharan, Cora Salm, and d Jurriaan Schmitz, " The Charge Plasma P-N Diode" IEEE ELECTRON DEVICE LETTERS, vol. 29, issue 12, pp 1367-1369, Dec 2008. doi: 10.1109/LED.2008.2006864 Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2021, the MOTIE (Ministry of Trade, Industry & Energy 20010836) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

Junctionless Silicon Nanotube Tunnel Field Effect Transistor Based Resistive Temperature Detector

A Junctionless Nanotube Tunnel Field Effect Transistor (JL-SiNT TFET) with platinum source and the aluminium gate electrode to enable band-to-band tunneling is proposed in this paper for significantly improved performance which is further used as an application of platinum resistive temperature detector according to earth’s environmental needs. The optimized device has been compared with the conventional Core-Shell Nanotube structure in view of analog parameters and electrical properties. High Ion/Ioff current ratio in the range of ~103, low subthreshold slopes, and high Ion current results in view of band-to-band tunneling induced in the device. Furthermore, we demonstrate that variations in the gate electrode work function, oxide thickness and silicon thickness can be used as design parameters to further upgrade the performance of the JL-SiNT TFET. The investigations showed that ON resistance of the sensor decreases in approximately by 2.3 times as the temperature increases from -200 °C to 200 °C. The resistance-temperature relationship shows high operability, high sensitivity, and the simulation is incongruent with the experimental results. The Nano Resistive temperature detector shows a sensitivity of −0.45%.

Modeling and Simulation of Ultrahigh Sensitive AlGaN/AlN/GaN HEMT-Based Hydrogen Gas Detector With Low Detection Limit

Presented through this work is a steady state analytical model of the GaN HEMT based gas detector. GaN with high chemical and thermal stability provides promises for detectors in hazardous environments. However, HEMT sensor resolution must be improved to develop high precision gas sensors for automotive and space applications. The proposed model aids in systematical study of the sensor performance and prediction of sensitivities. The linear relation of threshold voltage shift at thermal equilibrium is used in predicting the sensor response. Numerical model for the reaction rates and the electrical dipole at the adsorption sites at the surface and metal/semiconductor interface have been developed and the sensor performance is analyzed for various gas concentrations. The validation of the model has been achieved through surface and interfacial charge adsorption-based gate electrode work function, Schottky barrier, 2DEG and threshold voltage deduction using MATLAB and SILVACO ATLAS TCAD. Further the applicability of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{g}_{d}$ </tex-math></inline-formula> (channel conductance) as gas sensing metric is also presented. With high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{D}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{g}_{d}$ </tex-math></inline-formula> percentile sensitivities of 118.5% and 92 % for 10 ppm hydrogen concentration. The sensor shows capability for detection in sub-ppm levels by exhibiting a response of 0.043% for 0.01ppm (10 ppb) hydrogen concentration. The detection limit of the sensor (1% sensitivity) presented here is 169 ppb and the device current increases by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$34.2~\mu \text{A}$ </tex-math></inline-formula> for 1ppb hydrogen concentration.

Performance Analysis of Gate Electrode Work Function Variations in Double-gate Junctionless FET

With inherent structural simplicity due to the omission of ultrasteep p-n junctions, the conventional junctionless FET can be used as a barrier-controlled device with low OFF-current in the nanoscale regime. In this work, numerous performance parameters of conventional double-gate junctionless FET namely threshold voltage, OFF-current, ON-current, ON-to-OFF current ratio, and subthreshold slope have been investigated for the range of gate work function from 4.6 eV to 5.6 eV. The performance of conventional double-gate junctionless FET has been further improved with the proposed recessed double-gate junctionless FET using recessed silicon film in the channel region and it has been found that for the gate work function of 5.1 eV (mid-value) the proposed device shows OFF-current of the order of ~ 10− 14 A/µm, ON-to-OFF current ratio of the order of 1010 and subthreshold slope of 65.6 mV/dec as compared to the conventional double-gate junctionless FET. Interestingly, a range of work function values have been found to obtain the optimum performance from the conventional and proposed recessed double-gate junctionless FETs for low power applications. In the work function window, the variations in transconductance and gate-to-source capacitance for both junctionless devices have been illustrated. The impact of different values of the work function of the two gate electrodes for both junctionless devices has also been presented and it is found that the proposed device reflects robustness with nearly constant subthreshold slope.

Performance analysis of gate engineered dielectrically modulated TFET biosensors

ABSTRACT This paper presents, a short gate dual metal source electrode dielectrically modulated tunnel field-effect transistor (SDM SE DM-TFET) has been compared with conventional dual gate-source electrode dielectrically modulated tunnel field-effect transistor (DG SE DM-TFET) for the biosensing application. Hence, gate work function engineering is applied in our proposed device in which gate metal is split into two different work function segments as and . Additionally, a potential of −1.2 V is applied to the source electrode having a work function of . is the gate electrode work function at the source side and is the gate electrode work function at the drain side. The investigation is performed by varying the dielectric constant and charge density for choosing an optimised value for . The performance comparison has been done in terms of current, sensitivity and sensing speed. It can be verified from the simulated results that our proposed device exhibits superior performance as compared to the existing structures.

Subthreshold Performance Improvement of Underlapped FinFET Using Workfunction Modulated Dual-metal Gate Technique

Workfunction modulated dual material gate FinFET (WMDMG-FinFET) is proposed to improve the DC performance of the device. A dual metal gate FinFET with linear modulation in workfunction along the source side of gate electrode keeping drain side gate electrode workfunction to be constant is introduced. Its subthreshold performance (i.e., switching ratio and subthreshold swing) is enhanced by introducing spacers in the side-walls of gate, with underlap concept. SILVACO TCAD tool is used to carry out the simulation work. The simulation results are compared for different spacers and it is observed that TiO2 spacer with high-k dielectric gives the best switching ratio and lowest subthreshold swing. The WMDMG-FinFET with spacers in the underlapped region shows better subthreshold characteristics as compared to conventional DMG-FinFET.

Design and performance analysis of GAA Schottky barrier-gate stack-dopingless nanowire FET for phosphine gas detection

This paper proposed a Gate-All-Around (GAA) Schottky Barrier (SB)-Gate Stack (GS)-based Dopingless Cylindrical Nanowire Field-Effect Transistor (SB-GS-DNWFET) for the application of phosphine (PH3) gas detection. The Schottky barrier nanowire FET is used over a conventional nanowire FET at nanometer scale due to its inherent advantages such as low parasitic resistance and higher ON-state current. In this sensor, the changes in the work function of the metal gate electrode have been used for the detection amount of gas. Three different catalytic metals such as platinum, rhodium, and iridium are preferred as gate electrodes for PH3 gas detection because of their reactivity and sensitivity towards that gas. The sensitivity can be measured in terms of change in ON-state current (ION), subthreshold leakage current (IOFF), ON-state current-to-OFF-state current ratio (ION/IOFF), and threshold voltage (Vth) for sensing the gas molecules. The work function of these catalytic metals at gate electrode is varied as 50, 100, 150, and 200 meV to investigate the change in sensitivity parameters. In this work, the sensitivity of the Schottky barrier GAA-NWFET gas sensor with different catalytic metals (Pt, Rh, Ir) is compared and the impact of process parameters such as channel length and gate stacked (GS = SiO2 + high-k dielectric) on the sensitivity parameters is also studied.

Design Considerations and Capacitance Dependent Parametric Assessment of Gate Metal Engineered SiNW MOSFET for ULSI Switching Applications

This work investigates design consideration of Gate Electrode Workfunction Engineered (GEWE) silicon nanowire MOSFET at room temperature. It is perceived from the results that the parasitic capacitances are higher in the deep inversion region, however; the coupling of parasitic capacitance is weak in GEWE-SiNW due to lower gate metal workfunction at the drain end. Moreover, the influence of drain voltage on Cgs is very less owing to constant depletion charges at the source side which results in almost constant value of Cgs with the change in Vds. With tuning of channel length (Lg) and oxide thickness (tox), the effect of capacitances in GEWE-SiNW further reduces significantly due to quantization effect at such scaled dimensions. Furthermore, Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) have also been calculated with an aim to analyze the device DC and switching performance as they are directly or indirectly linked with parasitic capacitance. Calibrated 3D simulations validate that the GEWE-SiNW MOSFET exhibit 2.57, 34.5 and 2.75 times improvement in TFP, EDP and GBP respectively in comparison to SiNW in the linear region.