Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Abstract

This study describes a single‐gate silicon on insulator junctionless metal–oxide–semiconductor field‐effect transistor (SJL‐MOSFET) with inserted buried 4H‐SiC p‐type layer (B‐SJL‐MOSFET). The embedded p‐type layer is placed at the bottom of the active regions, achieving the full depletion of the channel in the off‐state mode. The p‐type layer affects the depletion region of the channel, which helps us have a full depletion area with a lower gate electrode work function. The main reason for using SiC material instead of silicon is the higher electrostatic integrity and a shorter natural length than silicon, resulting in a better short channel effect (SCE). In addition, the high‐k oxide is stacked for achieving lower natural length and better subthreshold swing (SS). The p‐type layer improves the leakage current (Ioff) by ≈105 in the event that it slightly diminishes the on‐state current (Ion) and improves the SS. Improvement of off‐current is due to higher barriers between source‐channel side and reduces the parasitic BJT in the off‐mode.