Metal Work Function Research Articles

Two-terminal vertical thyristor using Schottky contact emitter to improve thermal instability

In a two-terminal-electrode vertical thyristor, the latch-up and latch-down voltages are decreased when the memory operation temperature of the memory cells increases, resulting in a severe reliability issue (i.e. thermal instability). This study fundamentally solves the thermal instability of a vertical-thyristor by achieving a cross-point memory-cell array using a vertical-thyristor with a structure of vertical n++-emitter, p+-base, n+-base, and p++-emitter. The vertical-thyristor using a Schottky contact metal emitter instead of an n++-Si emitter significantly improves the thermal stability between 293 K and 373 K. Particularly, the improvement degree of the thermal stability is increased significantly with the use of the Schottky contact metal work function. Because the thermal instability (i.e. degree of latch-up voltage decrement vs. memory operation temperature) decreases with an increase in the Schottky contact metal work function, the dependency of the forward current density between the Schottky contact metal and p+-Si based on the memory operation temperature reduces with increase in the Schottky contact metal work function. Consequently, a higher Schottky contact metal work function produces a higher degree of improvement in the thermal stability, i.e. W (4.50 eV), Ti (4.33 eV), Ta (4.25 eV), and Al (4.12 eV). Further research on the fabrication process of a Schottky contact metal emitter vertical-thyristor is essential for the fabrication of a 3D cross-point memory-cell.

Fine-Grain Reconfigurable Logic Circuits for Adaptive and Secure Computing via Work-Function Engineered Schottky Barrier FinFETs

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky Barrier (SB) FinFETs for sub-10nm gate length. The study has three subsections. First, two-transistor (2T) & 4T AOI (and-or-invert)/ OAI (or-and-invert) gates with select bits that allow multiple logic functions are introduced. Secondly, the use of WFE to create ultra-compact reconfigurable logic circuits of fundamental operations (0,1,OR, AND,NAND,NOR,XOR) are explored via novel 2T, 3T and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multi-stage circuits such as compact full-adders are also modelled via TCAD simulations. Power×delay product (PDP) figures and DC gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact one-bit arithmetic logic unit (ALU) which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, Addition, Subtraction) with three select bits using only 26 SB-FinFETs, saving substantial amount of power and chip area. The trade-offs between the number of metal work-functions used in the designs, circuit complexity and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using ×3 to ×10 less power and between ×2 and ×15 less area than static CMOS counterparts. Although they suffer greater delays (×2 to ×5), the overall PDP performance remains comparable to conventional CMOS.

Numerical optimization of (FTO/ZnO/CdS/CH3NH3SnI3/GaAs/Au) perovskite solar cell using solar capacitance simulator with efficiency above 23% predicted

The presented study deals with the investigations of the methyl ammonium tin halide (CH3NH3SnI3) based perovskite solar cells for optimized device performance using solar capacitance simulations software. Several necessary parameters such as metal work functions, thickness of structural layers, charge carrier’s mobility and defect density have been explored to evaluate the device performance. Calculations reveal that for the best efficiency of device the maximum thickness of the perovskite (CH3NH3SnI3) absorber layer must be 4.2 μm. The thickness values of 0.01 μm for ZnO electron transport layer (ETL), 0.871 μm for GaAs hole transport layer and 0.001 μm for CdS buffer layer have been found which proved to be optimum for maximum power conversion efficiency (PCE) of 23.80% for the device. The variation of open circuit voltage (Voc), Short circuit current (Jsc), Fill Factor (FF %), quantum efficiency (QE) against thickness of all layers and interface defect densities in FTO/ZnO/CdS/CH3NH3SnI3/GaAs/Au composition have been critically explored and their crucial role for the device performance has been reported. Heterojunctions between ZnO-ETL and CdS buffer layers have shown improved device performance and PCE. Current investigations may prove to be useful for designing and fabrication of climate friendly, non-toxic and highly efficient solar cells.

Leakage mitigation in NW FET using negative Schottky junction drain and its process variation analysis

In this work, a Schottky junction on the drain side employing low workfunction (WF) metal is proposed as a method to suppress the OFF-state leakage in nanowire (NW) field-effect transistor (FET). Instead of a highly n+ doped drain, low WF metal with negative electron Schottky barrier height (SBH) as a drain minimizes the lateral band-to-band tunneling (L-BTBT) considerably. L-BTBT is the movement of carriers (holes) from the drain conduction band into the channel valence band during the OFF-state. Impact of varying WF at channel–drain junction on the device characteristics is studied. It is observed that SBH \(\leqslant 0\) eV is required to mitigate L-BTBT compared to the conventionally doped and junctionless (JL) NW counterpart. Furthermore, unlike L-BTBT, leakage in NW Schottky drain (SD) comprises of holes tunneling through the SB from the metal drain into the channel and is termed as the lateral SB tunneling (L-SBT). In contrast with JL NW FET, the process variation immunity (varying channel doping, \({N}_{\mathrm{Ch}}\) and NW diameter, \({d}_{\mathrm{NW}}\)) and the ON-state current of the proposed device are not compromised at the expense of lower OFF-state L-SBT. Instead, the device is less susceptible to process variations and retains the ON-state performance of the NW MOSFET. For a ± 20% change in \({N}_{\mathrm{Ch}}\), \(\Delta {I}_{\mathrm{OFF}}\)/\({I}_{\mathrm{OFF}}\) of 7% compared to 97% in NW JL FET is observed.

Optimization of Hole Transport Layer Materials for a Lead‐Free Perovskite Solar Cell Based on Formamidinium Tin Iodide

Recently, lead‐based perovskite solar cells have been mainly studied; however, these cells suffer from two main problems: the toxicity of lead and the instability of the devices, which limit their commercialization. Herein, a theoretical investigation of a lead‐free perovskite solar cell based on formamidinium tin iodide (HC(NH2)2SnI3) with the general architecture: glass/FTO/WS2/HC(NH2)2SnI3/HTL/Au is reported. All calculations are performed with the SCAPS‐1D solar cell simulator. Two inorganic (CuSCN and Cu2O) and two organic (P3HT and D‐PBTTT‐14) hole transport layer (HTL) materials are tested in this model. The effect of the external operating temperature and different metal work functions of the back contact of the cell on the overall performance of the devices is also studied. Simulations showed that, with the introduction of CuSCN, Cu2O, and P3HT as HTLs, the device can attain a remarkable efficiency of ≈21%. All the modeled devices showed remarkable performance of above 20% at higher temperatures of 380–420 K but degraded slightly when this range is exceeded. Relatively cheaper Pt, Ni, and Pd metals perform better, thus, can replace gold. These simulation results can provide avenues and directions for future advancement of the performance of lead‐free perovskite solar cells.

Efficient Sb2Se3 solar cell with a higher fill factor: A theoretical approach based on thickness and temperature

Antimony selenide, Sb2Se3, is a viable candidate for future generation solar cells because it is made from non-toxic, earth-abundant, and low-cost materials. Solar cells based on Sb2Se3 material have got worldwide attention because of their excellent power conversion efficiency. The simulation was carried out using the numerical simulation software SCAPS-1D (solar cell and capacitance simulator). The impact of temperature and thickness of absorber and buffer layer on the electrical properties of Sb2Se3 solar cells in terms of I-V, C-V measurements are reported. The simulated efficiency for Sb2Se3 with a back-contact metal work function of 5.1 eV at 200 K was observed to be 27.84%. As the temperature and thickness of the absorber layer rise from 200 to 350 K and 0.8–3.2 µm, respectively, the efficiency falls from 27.84% to 12.74%. The highest efficiency for Sb2Se3 solar cells is obtained with a radiative recombination coefficient value lower than 10−8 cm3/s. This work can help to improve the performance of Sb2Se3 based solar cells.

Towards high-efficiency planar heterojunction antimony sulfide solar cells

Recently, antimony sulfide (Sb2S3) based solar cells have received substantial attention, however their practical efficiency is far from ideal. Therefore, it is critical to provide numerical simulation on the devices, giving possible avenues to improve the performance. A planar heterojunction solar cell with a structure of FTO/electron transport layer (ETL)/Sb2S3/Cu2O/Au was investigated theoretically by Solar Cell Capacitance Simulator (SCAPS). The influence of different ETLs (CdS, TiO2, ZnO) and Cu2O layer has been firstly analyzed, and our results show that the best ETL is TiO2, and the device efficiency can be significantly increased when Cu2O is used as a hole transport layer (HTL). Then, the electron affinity of TiO2, Sb2S3 layer thickness, defect density, and metal work function on device performance have also been studied systematically. The best electron affinity of TiO2 is 3.6 eV, because a small positive conduction band offset (ΔEC = 0.1 eV) at the TiO2/Sb2S3 interface can be formed, enhancing carrier transport, and consequently, improving the device performance. Further, the optimal thickness for Sb2S3 layer is 200 nm when the defect density of the Sb2S3 layer is 1015 cm−3. To achieve ideal performance, the defect densities in the Sb2S3 layer and at the Sb2S3 interfaces should be as low as 1012 cm−3 and 2 × 1015 cm−2, respectively. In addition, the work function of the metal electrode larger than 4.9 eV is beneficial to device performance. Finally, a Sb2S3 solar cell with the conversion efficiency of 21.43% can be achieved after optimization, which performance is close to the conventional thin film solar cells. Our simulation results suggest the potential of Sb2S3 solar cells.

Simulating the performance of a high-efficiency SnS-based dual-heterojunction thin film solar cell

This article demonstrates a novel high efficiency ZnS/SnS/MoS2 dual-heterojunction thin film solar cell. The device has been optimized with respect to the thickness, doping concentration, and defect density of each constituent layer including working temperature and back contact metal work function using SCAPS-1D simulator. The MoS2 plays a promising role to serve as a back surface field (BSF) layer with commendatory band alignment, which provides an opportunity for higher absorption of longer wavelength photons utilizing the tail-states-assisted (TSA) two-step photon upconversion approach. The insertion of MoS2 in the ZnS/SnS pristine structure offers a significant improvement of the power conversion efficiency (PCE) within the detailed-balance limit with a rise from 20.1 to 41.4% with VOC of 0.91 V, JSC of 53.4 mA/cm2 and FF of 84.9%, respectively. This result reveals MoS2 as an effective BSF for low cost, highly efficient dual-heterojunction structure for future fabrication.

Electrical Performance Enhanced Doping Less Tunnel Field Effect Transistor by Metal Electrode Work Function Engineering

Tunnel field effect transistor (TFET) has been proposed as one of the promising alternative devices to MOSFET since it has low power consumption and excellent subthreshold swing (SS) characteristics of less than 60 mV / dec. However, conventional TFET fabrication requires ion implantation process to form p-i-n structure in active region, which induces a random distribution of dopant atoms. In the nm-scale device, even a small number of dopant atom dispersion can cause electrical characteristic variations such as threshold voltage (Vt)1, so alternative method for forming p-i-n region instead of doping process is needed.Doping-less TFET (DL-TFET) introduces charge plasma concept2 that controls carrier concentration of Si region by band alignment in MOS contact not by doping process, so random dopant fluctuation (RDF) issue can be solved. Since the active region carrier concentration is determined by the work function of the metal electrode, it is necessary to analyze the device performance by the metal work function condition. In this work, we manufactured doping-less TFET with adapting various metal work function to enhance electrical performance, and conducted CV measurement in MOS structure to confirm Si band bending and charge plasma by analyzing flat band voltage (VFB).DL-TFET was fabricated on SOI wafer and the overall structure is shown in Fig. 1. (a). In the case of the source region, the metal work function must be larger than that of Si to form the p-type active area, and drain region, on the contrary, must have smaller work function for n-type active region. Obviously, gate electrode work function has similar work function to intrinsic Si. For fabricating DL-TFET, we conducted reactive ion etch (RIE) process to define Si active layer and formed gate oxide (SiO2) by thermal oxidation. Then, we deposited gate metal and removed source / drain region oxide for contact hole. Spacer oxide was deposited using PECVD to isolate each metal electrode, finally we deposited source / drain metal. IV characteristics are shown in Fig. 1. (b), (c) when Pt / W / Al is applied at source / gate / drain area and we compared IV curve of various metal electrode and thermal conditions.In addition, to confirm whether the charge plasma was formed as intended, we fabricated MOS capacitor with 10 nm oxide thickness as shown in Fig. 1. (d). Through frequency sweep, we determined suitable bias frequency and conducted CV measurement (see Fig. 1. (e), (f), (g)). Band bending and charge plasma were confirmed by evaluating VFB shift depending on work function of each MOS gate material (see Fig. 1. (h)). Finally, we discussed the optimal metal electrode combination in terms of ambipolar current, off current, on current and SS. Key Words: Charge plasma, Doping-less TFET, Work function, CV measurement References Changho Shin, Jeong-Kyu Kim, Gwang-Sik Kim, Hyunjae Lee, Changhwan Shin, Jong-Kook Kim, Byung Jin Cho, and Hyun-Yong Yu, “Random Dopant Fluctuation-Induced Threshold Voltage Variation-Immune Ge FinFET With Metal–Interlayer–Semiconductor Source/Drain,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 63, No. 11, pp 4167-4172, Nov 2016. doi: 10.1109/TED.2016.2606511 Raymond J. E. Hueting, Bijoy Rajasekharan, Cora Salm, and d Jurriaan Schmitz, " The Charge Plasma P-N Diode" IEEE ELECTRON DEVICE LETTERS, vol. 29, issue 12, pp 1367-1369, Dec 2008. doi: 10.1109/LED.2008.2006864 Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2021, the MOTIE (Ministry of Trade, Industry & Energy 20010836) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

Screening and Understanding Li Adsorption on Two-Dimensional Metallic Materials by Learning Physics and Physics-Simplified Learning.

Understanding and broad screening Li interaction energetics with surfaces are key to the development of materials for a wide range of applications including Li-based electrochemical capacitors, Li sensors, Li separation membranes, and Li-ion batteries. In this work, we build a high-throughput screening scheme to screen Li adsorption energetics on 2D metallic materials. First, density functional theory and graph convolution networks are utilized to calculate the minimum Li adsorption energies for some 2D metallic materials. The data is then used to find a dependence of the minimum Li adsorption energies on the sum of ionization potential, work function of the 2D metal, and coupling energy between Li+ and substrate, and the dependence is used to screen all 2D metallic materials. Physics-simplified learning by splitting the property into different contributions and learning or calculating each component is shown to have higher accuracy and transferability for machine learning of complex materials properties.

Absorber layer optimisation of copper antimony sulfide thin film photovoltaics using numerical simulation

Recently, the ternary compound, CuSbS 2 , has been attracting a lot of interest in developing sustainable photovoltaic energy conversion because of its use as an absorber layer material due to the low toxicity, cost and abundance of constituents in nature. However, the recent conversion efficiencies reported for copper antimony sulfide (CAS) thin-film photovoltaics is still about 3%. Consequently, this research work is geared toward optimising the absorber layer material using numerical modelling and simulation to enhance the device performance. The simulation of the baseline model was achieved using the Solar Cell Capacitance Simulator (SCAPS-1D). Results of the simulation showed good agreement with experimental results. Subsequently, a step by step optimisation was done on the absorber layer. The optimisation process includes the variation of the acceptor concentration at various thicknesses, followed by the electron affinity and the back-contact metal work function. Results showed that the optimal carrier concentration of CuSbS 2 is 1 × 10 17 c m − 3 at a thickness of 2.6 μm. The electron affinity of 4.15 eV was obtained as the optimum value of the absorber. Also, it suggests that the back contact electrode optimal work function is 5.0 eV, which corresponds to that of Molybdenum. A combination of these optimisations doubled the recent experimentally obtained photo-conversion efficiency with a value of 7.42%. • The model Al: ZnO/CdS/CAS/Mo structure has been simulated SCAPS-1D software and results showed good agreements with experimental values. • The optimal carrier concentration of CuSbS 2 was observed to be at 1 × 10 17 c m − 3 at a thickness of 2.6 μm. • Further optimisation of the absorber's electron affinity of 4.15 eV and the back-contact metal work function of 5.0 eV enhanced the device performance. • A combination of these optimizations doubled the experimentally obtained photo-conversion efficiency with a value of 7.42%.

Molecule-Upgraded van der Waals Contacts for Schottky-Barrier-Free Electronics.

The applications of any ultrathin semiconductor device are inseparable from high-quality metal-semiconductor contacts with designed Schottky barriers. Building van der Waals (vdWs) contacts of 2D semiconductors represents an advanced strategy of lowering the Schottky barrier height by reducing interface states, but will finally fail at the theoretical minimum barrier due to the inevitable energy difference between the semiconductor electron affinity and the metal work function. Here, an effective molecule optimization strategy is reported to upgrade the general vdWs contacts, achieving near-zero Schottky barriers and creating high-performance electronic devices. The molecule treatment can induce the defect healing effect in p-type semiconductors and further enhance the hole density, leading to an effectively thinned Schottky barrier width and improved carrier interface transmission efficiency. With an ultrathin Schottky barrier width of ≈2.17nm and outstanding contact resistance of ≈9 kΩµm in the optimized Au/WSe2 contacts, an ultrahigh field-effect mobility of ≈148cm2 V-1 s-1 in chemical vapor deposition grown WSe2 flakes is achieved. Unlike conventional chemical treatments, this molecule upgradation strategy leaves no residue and displays a high-temperature stability at >200 °C. Furthermore, the Schottky barrier optimization is generalized to other metal-semiconductor contacts, including 1T-PtSe2 /WSe2 , 1T'-MoTe2 /WSe2 , 2H-NbS2 /WSe2 , and Au/PdSe2 , defining a simple, universal, and scalable method to minimize contact resistance.

Design and Self-Consistent Schrodinger-Poisson Model Simulation of Ultra-Thin Si-Channel Nanowire FET

Since at the regime of nanometer, the quantum confinement effects are observed and the wave nature of electrons is more dominant. Therefore, the classical approach of current formulation in mesoelectonics and nanoelectronics results in inaccuracy as it does not consider the quantum effect, which is only applicable for the bulk electronic device. For accurate modeling and simulation of nanoelectronics, device atomic-level quantum mechanical models are required. In this work, an ultra-thin (2 nm diameter) Silicon- channel Cylindrical Nanowire FET (CNWFET) is designed and simulated by invoking non-equilibrium green function (NEGF) formalism and self-consistent Schrodinger-Poisson’s equation model. Then impact variation of temperature, oxide thickness, and metal work function variation in the NWFET is investigated to analyze the distinct performance parameters of the device e.g. threshold voltage (Vth) drain induced barrier lowering (DIBL), sub-threshold swing (SS), and ION/IOFF ratio. The designed device exhibits reliable results and shows a SS of 57.8 mV/decade and ION to IOFF ratio of order 109 at room temperature.

Ab Initio Study of Hexagonal Boron Nitride as the Tunnel Barrier in Magnetic Tunnel Junctions.

Two-dimensional hexagonal boron nitride (h-BN) is studied as a tunnel barrier in magnetic tunnel junctions (MTJs) as a possible alternative to MgO. The tunnel magnetoresistance (TMR) of such MTJs is calculated as a function of whether the interface involves the chemi- or physisorptive site of h-BN atoms on the metal electrodes, Fe, Co, or Ni. It is found that the physisorptive site on average produces higher TMR values, whereas the chemisorptive site has the greater binding energy but lower TMR. It is found that alloying the electrodes with an inert metal-like Pt can induce the preferred absorption site on Co to become a physisorptive site, enabling a higher TMR value. It is found that the choice of physisorptive sites of each element gives more Schottky-like dependence of their Schottky barrier heights on the metal work function.

Analysis of Hybrid Hetero-Homo Junction Lead-Free Perovskite Solar Cells by SCAPS Simulator

In this work, we report on the effect of substituting the active intrinsic i-layer on a conventional pin structure of lead-free perovskite solar cell (PSC) by a homo p-n junction, keeping the thickness of the active layer constant. It is expected that when the active i-layer is substituted by a p-n homo junction, one can increase the collection efficiency of the photo-generated electrons and holes due to the built-in electric field of the homo junction. The impact of the technological and physical device parameters on the performance parameters of the solar cell have been worked out. It was found that p-side thickness must be wider than the n-side, while its acceptor concentration should be slightly lower than the donor concentration of the n-side to achieve maximum efficiency. In addition, different absorber types, namely, i-absorber, n-absorber and p-absorber, are compared to the proposed pn-absorber, showing a performance-boosting effect when using the latter. Moreover, the proposed structure is made without a hole transport layer (HTL) to avoid the organic issues of the HTL materials. The back metal work function, bulk trap density and ETL material are optimized for best performance of the HTL-free structure, giving Jsc = 26.48, Voc = 0.948 V, FF = 77.20 and PCE = 19.37% for AM1.5 solar spectra. Such results highlight the prospective of the proposed structure and emphasize the importance of using HTL-free solar cells without deteriorating the efficiency. The solar cell is investigated by using SCAPS simulator.

Tailoring the Interfacial Band Offset by the Molecular Dipole Orientation for a Molecular Heterojunction Selector.

Understanding and designing interfacial band alignment in a molecular heterojunction provides a foundation for realizing its desirable electronic functionality. In this study, a tailored molecular heterojunction selector is implemented by controlling its interfacial band offset between the molecular self‐assembled monolayer with opposite dipole orientations and the 2D semiconductor (1L‐MoS2 or 1L‐WSe2). The molecular dipole moment direction determines the direction of the band bending of the 2D semiconductors, affecting the dominant transport pathways upon voltage application. Notably, in the molecular heterostructure with 1L‐WSe2, the opposite rectification direction is observed depending on the molecular dipole moment direction, which does not hold for the case with 1L‐MoS2. In addition, the nonlinearity of the molecular heterojunction selector can be significantly affected by the molecular dipole moment direction, type of 2D semiconductor, and metal work function. According to the choice of these heterojunction constituents, the nonlinearity is widely tuned from 1.0 × 101 to 3.6 × 104 for the read voltage scheme and from 0.4 × 101 to 2.0 × 105 for the half‐read voltage scheme, which can be scaled up to an ≈482 Gbit crossbar array.

A simulation study of perovskite based solar cells using CZTS as HTM with different electron transporting materials

In this manuscript, we have performed the device modeling on perovskite based solar cells (PSC,s) to investigate the potential of different hole transport materials (HTM’s) in combination with electron transport materials (ETM) using SCAPS 3.3 software package. Our simulated results depict that in the case of PSCs with CZTS, various parameters such as Voc, FF and PCE have demonstrated their maximum values at HTM thickness 700nm. It is further observed that the increase thickness of absorber layer resulted in the significant improvement of different performance parameters at specific limit then become constant. Moreover, studies of metal contact exposed that by increasing the work function of front contact of PSC efficiency decline to 7.34%. Optimized value of FTO front contact and Ni back contact metal work function were found to be 4.4 and 5.35 eV respectively. But at higher value of defect density in the PSCs, the performance of the cell is independent of thickness. At the carrier concentration of ETM is 1018 cm-3 , ZnO and TiO2 have PCE 12.52 and 12.69 % respectively.

Study on the Characteristics of Schottky Temperature Detector Based on Metal/n-ZnO/n-Si Structures

Background: At present, the main problems of Micro-Electro-Mechanical Systems (MEMS) based temperature detector are the narrow range of temperature detection and difficulty in the measurement of high temperature. Besides, MEMS devices have different response characteristics for various surrounding temperature in the petrochemical and metallurgy application fields with hightemperature and harsh conditions. To evaluate the performance stability of the high-temperature MEMS devices, the real-time temperature measurement is necessary. Objective: A Schottky temperature detector based on the metal/n-ZnO/n-Si structures is designed to measure high temperature (523~873K) for MEMS devices with a large temperature range. Methods: By using the Finite Element Method (FEM), three different work function metals (Cu, Ni and Pt) contacting the n-ZnO were investigated to realize Schottky. At room temperature (298K) and high temperature (523~873K), the current densities with various bias voltages (J-V) were studied. Results: The simulation results show that the high-temperature response power consumption of three Schottky detectors of Cu, Ni and Pt decreases successively, which is 1.16 mW, 63.63 μW and 0.14 μW. The response temperature sensitivities of 6.35 μA/K, 0.78 μA/K, and 2.29 nA/K are achieved. Conclusion: The Cu/n-ZnO/n-Si Schottky structure could be used as a high-temperature detector (523~873K) for the high-temperature MEMS devices. It has a large temperature range (350K) and a high response sensitivity of 6.35 μA/K. Compared with the traditional devices, the Cu/n-ZnO/n-Si Schottky structure-based temperature detector has a low energy consumption of 1.16 mW, having potential applications in the high-temperature measurement of the MEMS devices.

Reverse-Offset Printing of Polymer Resist Ink for Micrometer-Level Patterning of Metal and Metal-Oxide Layers.

Printed electronics has advanced during the recent decades in applications such as organic photovoltaic cells and biosensors. However, the main limiting factors preventing the more widespread use of printing in flexible electronics manufacturing are (i) the poor attainable linewidths via conventional printing methods (≫10 μm), (ii) the limited availability of printable materials (e.g., low work function metals), and (iii) the inferior performance of many printed materials when compared to vacuum-processed materials (e.g., printed vs sputtered ITO). Here, we report a printing-based, low-temperature, low-cost, and scalable patterning method that can be used to fabricate high-resolution, high-performance patterned layers with linewidths down to ∼1 μm from various materials. The method is based on sequential steps of reverse-offset printing (ROP) of a sacrificial polymer resist, vacuum deposition, and lift-off. The sharp vertical sidewalls of the ROP resist layer allow the patterning of evaporated metals (Al) and dielectrics (SiO) as well as sputtered conductive oxides (ITO), where the list is expandable also to other vacuum-deposited materials. The resulting patterned layers have sharp sidewalls, low line-edge roughness, and uniform thickness and are free from imperfections such as edge ears occurring with other printed lift-off methods. The applicability of the method is demonstrated with highly conductive Al (∼5 × 10–8 Ωm resistivity) utilized as transparent metal mesh conductors with ∼35 Ω□ at 85% transparent area percentage and source/drain electrodes for solution-processed metal-oxide (In2O3) thin-film transistors with ∼1 cm2/(Vs) mobility. Moreover, the method is expected to be compatible with other printing methods and applicable in other flexible electronics applications, such as biosensors, resistive random access memories, touch screens, displays, photonics, and metamaterials, where the selection of current printable materials falls short.

Mitigating the charge trapping effects of D-sorbitol/poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) polymer blend contacts to crystalline silicon

Abstract Solution-processable conductive polymers are advantageous materials for making inexpensive, electrical junctions to crystalline semiconductors. We have investigated methods to improve the device performance of hybrid solar cells made from n-type silicon and a conductive polymer glue based on a blend of poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) and D-sorbitol. The PEDOT:PSS blend behaves like a high work function metal creating a Schottky-type junction. The addition of D-sorbitol increases PEDOT:PSS conductivity and provides adhesive properties, allowing the top contact of the solar cell to be laminated onto the silicon substrate. Unfortunately, the addition of the D-sorbitol to the PEDOT:PSS significantly alters the shape of the measured current-voltage performance curve of a crystalline silicon (n-Si)/PEDOT:PSS junction. Under illumination, this results in a decline in the fill factor (FF) and a drop in photocurrent density (J sc) compared to PEDOT:PSS-only devices. We have discovered that the decline in device performance is likely due to surface trap states caused by D-sorbitol/silicon interaction and/or silicon oxidation. X-ray photoelectron spectroscopic (XPS) analysis shows that surface oxidation quickens, and possible silicon surface functionalization with D-sorbitol occurs while processing the D-sorbitol/PEDOT:PSS contact on H-terminated surfaces. To overcome these interface issues, the silicon surface was chemically modified using surface methylation, making it insensitive to D-sorbitol/silicon interactions and surface oxidation during the processing of the PEDOT:PSS polymer blend contact. This also enabled the crystalline silicon (n-Si)/s-PEDOT:PSS device performance to be maintained for longer periods. Using a silicon surface methylation strategy, good device performance could be achieved without changing the adhesive properties of D-sorbitol/PEDOT:PSS polymer blend.