Abstract

Since at the regime of nanometer, the quantum confinement effects are observed and the wave nature of electrons is more dominant. Therefore, the classical approach of current formulation in mesoelectonics and nanoelectronics results in inaccuracy as it does not consider the quantum effect, which is only applicable for the bulk electronic device. For accurate modeling and simulation of nanoelectronics, device atomic-level quantum mechanical models are required. In this work, an ultra-thin (2 nm diameter) Silicon- channel Cylindrical Nanowire FET (CNWFET) is designed and simulated by invoking non-equilibrium green function (NEGF) formalism and self-consistent Schrodinger-Poisson’s equation model. Then impact variation of temperature, oxide thickness, and metal work function variation in the NWFET is investigated to analyze the distinct performance parameters of the device e.g. threshold voltage (Vth) drain induced barrier lowering (DIBL), sub-threshold swing (SS), and ION/IOFF ratio. The designed device exhibits reliable results and shows a SS of 57.8 mV/decade and ION to IOFF ratio of order 109 at room temperature.

Highlights

  • The demand to scale down MOSFET to increase the chip density with high performance has forced the researcher to look for another device as MOSFET has reached its physical limit [1]

  • In 2010, Cheung et al stated that the subthreshold swing of MOSFETs can never be below 60mV/decade at room temperature [2]

  • The limitation of the sub-threshold swing will lead to high leakage current even in the OFF state resulting in static power dissipation which may result in the thermal runway of the electronic device [6, 7]

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Summary

Introduction

The demand to scale down MOSFET to increase the chip density with high performance has forced the researcher to look for another device as MOSFET has reached its physical limit [1]. The limitation of the sub-threshold swing will lead to high leakage current even in the OFF state resulting in static power dissipation which may result in the thermal runway of the electronic device [6, 7]. Since the main aim is a small-sized transistor with high performance and low power consumption, many changes in MOSFET structure and MOSFET-like structure were done and but with persistent short channel effects, the parasitic capacitance was observed and very little improvement in the subthreshold swing was achieved [9,10,11]. The study and simulation of the nanoscaled devices are challenging as at nanoscale regime, the transistor operates near the ballistic limit, electron-hole pairs are generated by the band to band tunneling despite thermal emission and show quantum effects [15, 16]

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