Wire Bond Research Articles

A Systematic Approach to Reduce Wirebond defects caused by Tight Wire Loop Profile on Ball Grid Array Packages

Wirebond quality aspects on a semiconductor manufacturing is one of the key factors to be considered in having a robust product. Certain criteria are defined, met, and affects the output on the product. Other variables from downstream process are also taken in account to affect the response, specific die position or placement on die attach is one example. Without controlling this input factor, unwanted out of specification response will occur and may result to rejections on the next process. This paper will focus on how to address the wire tight loop on wire bond process by analyzing the problem through systematic approach using statistical tools improving the current performance of die placement on BGA products.

Research on the Influence of Bond Wire Lift-Off Position on the Electro-Thermal Characteristics of IGBT

Based on the actual packaging structure of insulated gate bipolar transistor (IGBT) module, this article establishes the power loss model, and analyzes the influence of the position of the lift-off bond wire on the module. Through the theoretical analysis, it is found that the position of the lift-off bond wire is an important factor affecting the aging of the modules. And then the electrothermal coupling model of IGBT is established for simulation, and an experimental platform is built for verification. The results show that the distribution of bond wire lift-off position is one of the characteristics of bond wire failure. When the bond wire lift-off failure is concentrated on a single IGBT chip, it will accelerate the aging process of the modules. Therefore, this article considers that the position of the lift-off bond wire is a significant factor in the aging process of the modules, which should be fully considered in the bond wire state evaluation. In addition, the research results of this article can also provide theoretical reference for the optimization of IGBT module packaging structure.

Interleaved Planar Packaging Method of Multichip SiC Power Module for Thermal and Electrical Performance Improvement

Double-sided cooling based on planar packaging method features better thermal performance than traditional single-sided cooling based on wire bonds. However, this method still faces thermal and electrical challenges in multichip SiC power modules. Specifically, one is severe thermal coupling among parallel bare dies, and the other is unbalanced current sharing due to unreasonable layout design. This article aims to explore the potentials of SiC power devices in power module, which are higher current capability and reliability. The proposed packaging method is called interleaved planar packaging and can get rid of the optimizing contradiction between thermal and electrical performance. In this packaging method, there are two functional units: interleaved switch unit and current commutator structure. Benefited from the two units’ electromagnetic and thermal decoupling effects, the interleaved power module features low loop inductance, balanced current, low coupling thermal resistance, and even thermal distributions. A 1200 V 3.25 mΩ half-bridge SiC power module based on interleaved planar packaging is fabricated and tested to verify this method's superiority.

Regional Pulsewidth and Delay Nonuniformity of Modulated 940 nm Vertical‐Cavity Surface‐Emitting Laser Array

Under pulsed modulation, the emission uniformity in terms of pulsewidth and delay of a 940 nm multimode vertical‐cavity surface‐emitting laser (MM‐VCSEL) array is characterized by analyzing the position‐dependent pulsating and chirping dynamics among localized 600 VCSEL elements. In addition, the MM‐VCSEL array biased nearly threshold current (Ith) of 350 mA with a low resistance of 0.72 Ω reveals serious impedance mismatching with a high reflection coefficient (Γ) of −0.97. The MM‐VCSEL array biased below threshold (at Idc: ≈0.9 Ith) reveals low‐impedance and high‐capacitance behavior to result in large modulation reflection with allowable −3 dB bandwidth of 0.8 GHz. The nonuniform optical intensity and delay distribution among all MM‐VCSEL elements corroborate that the gradually enlarged inductance attenuates the modulation current away from bond wires. By modulating the 0.9Ith‐biased MM‐VCSEL array with an 127 ps‐wide electrical pulse with a peak amplitude of 15.3 V, a multimode fiber probe collects the single MM‐VCSEL output with average power, peak voltage, and pulsewidth of 0.08 mW, 25.1 mV, and 602 ps. The delay time as large as 273.4 ps between the nearest and farthest parts of local MM‐VCSEL elements in the array determines its impulse response and uniformity for applications.

Characterization of Wire-Bonding on LDS Materials and HF-PCBs for High-Frequency Applications

Thermosonic wire bonding is a well-established process. However, when working on advanced substrate materials and the associated required metallization processes to realize innovative applications, multiple factors impede the straightforward utilization of the known process. Most prominently, the surface roughness was investigated regarding bond quality in the past. The practical application of wire bonding on difficult-to-bond substrates showed inhomogeneous results regarding this quality characteristic. This study describes investigations on the correlation among the surface roughness, profile peak density and bonding quality of Au wire bonds on thermoplastic and thermoset-based substrates used for high-frequency (HF) applications and other high-end applications. FR4 PCB (printed circuit board flame resitant class 4) were used as references and compared to HF-PCBs based on thermoset substrates with glass fabric and ceramic filler as well as technical thermoplastic materials qualified for laser direct structuring (LDS), namely LCP (liquid crystal polymer), PEEK (polyether ether ketone) and PTFE (polytetrafluoroethylene). These LDS materials for HF applications were metallized using autocatalytic metal deposition to enable three-dimensional structuring, eventually. For that purpose, bond parameters were investigated on the mentioned test substrates and compared with state-of-the-art wire bonding on FR4 substrates as used for HF applications. Due to the challenges of the limited thermal conductivity and softening of such materials under thermal load, the surface temperatures were matched up by thermography and the adaptation of thermal input. Pull tests were carried out to determine the bond quality with regard to surface roughness. Furthermore, strategies to increase reliability by the stitch-on-ball method were successfully applied.

A Survey of Detection Methods for Die Attachment and Wire Bonding Defects in Integrated Circuit Manufacturing

Defect detection plays a vital role in the manufacturing process of integrated circuits (ICs). Die attachment and wire bonding are two steps of the manufacturing process that determine the power and signal transmission quality and dependability in an IC. This paper presents a survey or literature review of the methods used for detecting these defects based on different sensing modalities used including optical, radiological, acoustical, and infrared thermography. A discussion of the detection methods used is provided in this survey. Both conventional and deep learning approaches for detecting die attachment and wire bonding defects are considered along with challenges and future research directions.

The Bigger Level Of Blood Lead, The Higher Level Of SGOT and SGPT In Residents Around The Used Battery Recycling Industry

Hazardous materials that need to be watched out for are exposure to lead (Pb) in solder wire from the used battery recycling industry. Pb can cause health problems for workers and the community around the high risk industry. Exposure occurs through inhalation, ingestion or skin because Pb is a multi-media pollutant. Abnormal levels of Pb in the blood have a risk of 1,783 times, can reach toxic levels and cause disturbances in the soft tissues of the liver, characterized by increased levels of SGOT and SGPT in the blood. The purpose of this study was to determine the relationship between blood lead levels and SGOT & SGPT levels in residents around the used battery recycling industry. The number of research samples as many as 40 respondents through the analytical method of observational cross-sectional design approach. Sampling was done by non-probability sampling with purposed sampling technique. The results showed that Pb levels reached 695.90 ug/L exceeds the value of the biological exposure index (IPB). There is a relationship between blood lead levels and blood SGOT& SGPT levels (p = 0.003) and (p = 0.000) with a strong positive relationship (r = 0.460)and (r = 0.526). The conclusion is that there is a relationship between blood lead levels and SGOT & SGPT levels in residents around the used battery recycling industry and the greater the blood Pb level, the higher the SGOT & SGPT levels.

Effects of electrolyte towards copper wire metallurgical interconnection in semiconductor

Copper (Cu) wire has been extensively used in the semiconductors industry to replace gold wire because of its cost-effectiveness and high performance. However, it has a massive challenge because of its high oxidation rate, high hardness, and high susceptibility to corrosion which is time-sensitive under environmental conditions. One of the attractive factors to investigate is the electrolytes used in the assembly process of copper wire. However, these electrolyte chemicals may potentially affect the quality of the copper wire bond’s metallurgical interconnection, manifesting as copper corrosion. Therefore, this paper will investigate the mechanism of the electrolyte reaction and the chemicals. In addition, the metallurgical morphology of the copper wire observes through electron microscopy. The results suggest that corrosion occurs with a specific time rate, electrolyte type-dependent and metallurgical interconnection system. The Copper wire bonded on silver (Ag) plated lead frame (Cu-Ag-Cu) interconnection experiences a significant morphological change in most compared with other electrolyte systems. Furthermore, since it is a bimetallic element (Cu and Ag) thus, the corrosion type is galvanic.

Design of Low Inductance SiC-MOS/Si-IGBT Hybrid Module for PV Inverters

In this paper, design of a low parasitic inductance T-type SiC-MOS/Si-IGBT hybrid module for PV inverters is studied. Current commutation loops and self- and mutual inductances model of the hybrid module are analyzed. Then stacked substrates structures with vertical power commutation loop to reduce parasitic inductance are identified and compared. Finally, a hybrid module with stacked bond wire substrates structure is built and test results are provided to verify the design.

In Situ Junction Temperature Monitoring and Bond Wire Detecting Method Based on IGBT and FWD on-State Voltage Drops

Junction temperature monitoring and bond wire detection are crucial for the condition monitoring and protection of insulated gate bipolar transistor (IGBT) and freewheeling diode (FWD). <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state voltage drop is one of the most popular parameters for junction temperature estimation and bond wire detection. However, there is still a lack of cost-effective <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state voltage drop measuring techniques for both IGBT and FWD with a fast response. This article proposes an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> junction temperature monitoring and bond wire detecting method based on IGBT and FWD <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state voltage drops. The proposed technique can measure the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state voltage drops of IGBT and FWD online with high accuracy and fast response. The <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state voltage drops of IGBT and FWD under low load current are linearly dependent on their junction temperatures. Besides, the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state voltage drops under high load current are closely related to the bond wire degradation. Therefore, the junction temperatures and bond wire conditions of both IGBT and FWD can be monitored based on the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state voltage drops during a period of alternating current. The experiment results validate the feasibility of the proposed <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state voltage drop-based method for junction temperature monitoring and bond wire detecting. The proposed method has characteristics of high response speed, noninvasiveness for normal converter operating, and simple structure.

Aging Monitoring Method of Bond Wires-Based on Phase-Frequency Characteristics of Differential Mode Conducted Interference Signal for IGBT Module

This paper presents an on-line monitoring method of IGBT module bond wires aging based on the phase-frequency characteristics (PFCs) of differential mode (DM) interference signal. Firstly, the collector current variation during IGBT chip switching is analyzed, and the relationship between the aging degree of bond wires and the PFCs of DM interference signal is studied; Secondly, a phase angle characteristic measurement system of DM interference signal is built and used to online monitor the aging of bond wires in IGBT module; Finally, taking the buck converter composed of IGBT module as the equipment under tested, the interference signal is extracted by the RF current probe and processed by the low-pass filter and signal amplifier, then the phase angle characteristics are measured by the oscilloscope board to realize the on-line monitoring of the bond wires aging of IGBT module. The experimental results show that compared with buck converter with healthy IGBT module, the phase angle of DM interference signal in Buck Converter with aging IGBT module is reduced. The proposed method does not need expensive equipment such as spectrum analyzer, and only needs to monitor the aging state of bond wires in IGBT module online through oscilloscope board. Besides, the research method in this paper provides an approximate linear monitoring method for bonding wire lift-off.

1200 V/650 V/160 A SiC+Si IGBT 3L Hybrid T-Type NPC Power Module With Enhanced EMI Shielding

Three-level (3L) inverters suffer from higher parasitic inductance due to the increased number of series-connected switches in a single current commutation loop (CCL) results in a larger size of CCL compared to their two-level (2L) counterparts. As such, semiconductors are subjected to higher voltage stress and severe ringing at the switching transient. While silicon carbide's (SiC) faster switching speed improves overall efficiency by reducing switching loss, the faster voltage, and current gradient (dv/dt and di/dt) generate electromagnetic interference (EMI) noise, requiring a larger and complicated filter stage design. To solve this problem, an optimized 3L T-type neutral point clamped power module has been proposed with a hybrid combination of the switch (SiC mosfet + Si IGBT) rated for 1200 V/160 A. Two direct bonded copper (DBC) substrates have been stacked to have a vertical power loop using laser-drilled vias, which provides low commutation loop inductance as low as 4.6 nH for the major CCLs including the wire bond. Other associated CCLs have also been identified and optimized. Additional DBC in the package will be acting as an EMI shield. The EMI noise has been compared to a traditional power module and a 21 dB reduction of common-mode noise has been observed.

Degradation mechanism analysis for SiC power MOSFETs under repetitive power cycling stress

In this work, investigation on the degradation behavior of 1.2 kV/52 A silicon carbide (SiC) power MOSFETs subjected to repetitive slow power cycling stress has been performed. Electric characteristics have been characterized periodically over the stress and the respective degradation mechanisms have also been analyzed. A comprehensive degradation analysis is further conducted after the aging test by virtue of the x-ray inspection system, scanning acoustic microscope, scanning electron microscope, emission microscope, etc. Experimental results reveal that both the degradation of the gate oxide on the chip-level and the degradation of the bond wire and solder layer on the package-level have emerged over the cyclic stress. Specifically, growths of threshold voltage (V th) and gate leakage current (I gss) are thought to be relevant with the degradation of gate oxide by SiC/SiO2 interface states trapping/de-trapping electrons on the chip-level, while the appearance of fatigue in the bond wire and the delamination of the solder layer imply the degradation on the package-level. This work may provide some practical guidelines for assessments of the reliability of SiC power MOSFETs in power conversion systems.

RF Performance Benchmarking of TSV Integrated Surface Electrode Ion Trap for Quantum Computing

Surface electrode ion trap is highly promising for practical quantum computing due to its superior controllability on the trapped ions. With advanced microfabrication techniques, silicon has been developed as an ion trap substrate for delicate surface electrodes design and monolithic electro-optical components integration. However, the high RF loss of silicon hinders the possible large-scale implementation. In this work, we demonstrate a through silicon via (TSV) integrated ion trap, which has low RF loss due to the elimination of wire bonding (WB) pads on the surface and the miniaturization of form factor. We also fabricate two types of conventional WB traps with or without a grounding screen layer. The RF performances of different ion traps are tested and compared, in terms of on-chip S-parameter, postpackaging resonance, and resulting power loss. The results show that the TSV trap has low S21 (~0.2 dB at 50 MHz), high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> factor (~22), and low power loss (0.26 W) compared to WB traps. In addition, 3-D finite element modeling (FEM) is employed for electric field visualization and RF loss analysis of different traps. The extracted results from the modeling show a decent agreement with the measurements. In addition to various RF tests, the design, fabrication, and ion trapping operation of different ion traps are presented. This work provides insights into RF loss of ion trapping devices and offers a new solution for RF loss reduction.

Failure Modes in Microfabricated Ion Trap Devices for Quantum Information Science

Abstract Trapped ion systems are one of the leading technology platforms for quantum computing. This article describes the construction and operation of ion trap devices and the various modes of failure that have been observed. Examples of failure in either the rendering or use of packaged trap chips are presented, including electrode shorts and opens, detached bond wires, and RF breakdown damage.

High-Frequency Non-Invasive Magnetic Field-Based Condition Monitoring of SiC Power MOSFET Modules

Current distribution anomaly can be used to indicate the onset of package-related failures modes in Silicon Carbide power MOSFET modules. In this paper, we propose to obtain the wire bond’s magnetic field profile using an array of Tunnel Magneto-Resistance (TMR) sensors, and characterise the small changes in the current density distribution to find the onset of the wire bond degradation processes, including wire bond lift-off, wire bond cracking, and wire bond fracture. We propose a novel condition monitoring technique where a non-galvanic high-bandwidth sensing and a reliability model monitor the health of the power switches. We designed a dedicated calibration set-up to examine the sensor array and calibrated to demonstrate the adequate sensitivity to a minimum 5% current anomaly detection in a single wire bond of the switching devices operating with 50 kHz switching frequency. We use a hardware-in-the-loop (HIL) experimental set-up to replicate wire bond-related failures in a 1200 V/55 A SiC MOSFET power module of a DC/DC Boost converter. Signal conditioning circuits are further designed to amplify and buffer the sensor readings. Experimental results showed the proposed technique is able to detect a wide range of package-related failures.

Impact of heat treatment on the lifetime of wire-bonded power modules

Wire bondings in power modules are one of the weakest links in packaging, often causing an entire power module to fail. Thermo-mechanical stresses in the wire bonds related to CTE mismatch induce cracks that propagate in a region close to the bonding interface. In this paper, Scanning Electron Microscope (SEM) analysis after a bonding process clearly shows small grains and a different texture close to the interface of the wire and the die metallization. In order to improve the reliability of wire bonds, heat treatment after power module manufacturing is proposed. Heat treatment has a positive effect on the bonding region by increasing the grain size, reducing the dislocation density and merging the grains of the wire and the metallization. Furthermore, power cycling has been shown to increase the lifetime of the heat-treated power modules compared to a control comprising the same non-treated (as-delivered) IGBT power modules.

Relative importance of solder and wire bond defects on the maximum junction temperature of IGBT devices

The wear-out of interconnection packaging materials of Insulated-Gate Bipolar Transistors (IGBTs) during power cycling in Pulse Width Modulation (PWM) mode can induce a local temperature increase on the die surface, resulting in thermal runaway, and ultimately short-circuit failure. In this study, the effect of PWM power cycling on solder and wire bond aging states as well as on the surface temperature distribution and thermal resistance was measured by infrared camera and compared with microstructural analysis. Horizontal cracks in the solder close to the solder-die interface induced the highest thermal resistance increase. Comparatively, the impact of solder voids on the thermal resistance was lower, but this caused significant bow of the die due to solder redistribution. This may contribute to an increased stress intensity factor at the die edges and thus horizontal crack formation. Lift-off bonds can also locally increase the die surface temperature due to Joule heating at imperfect electrical contacts. Analytical expressions validated by measurements and electro-thermal Finite Element Modeling were developed to estimate the relative importance of the different defects for a wider range of module designs and operating conditions.

Online monitoring of IGBT modules based on creating the non-interventional monitoring environment

Aiming at the health monitoring of IGBT modules based on the online measurement of junction temperature Tj and the saturated voltage drop VCE in the three-level neutral-point-clamped (3LNPC) inverter, this paper puts forward the idea of creating a suitable monitoring environment to inject monitoring current without affecting the normal operation of the inverter. Based on this method, not only the online monitoring can be performed at different moments, but also the monitoring duration can be selected according to monitoring requirements. Meanwhile, the online monitoring will not distort the load current of the inverter. In this paper, an online monitoring experiment platform has also been designed to realize the monitoring current injection, the saturated voltage drop VCE sampling, and the sampling data transmission. The results of simulation and experiment verify the safety and the non-intervention of the online monitoring process, and the data collected by DSP during monitoring is used to judge whether the bond wires of IGBT module are failed.

Analytical modeling of thermo-mechanical stress for bond wire of IGBT module

Reliability of bond wires in power modules has been a main subject of interest in both industry and academia. Until now, analytical modeling of thermo-mechanical stress mainly focuses on the loop height variation of bond wires instead of plastic strain, which is the key factor causing the fatigue failure. In this paper, an analytical model for analyzing plastic strain of bond wires in IGBT modules is proposed. Using a laser displacement sensor, the dynamic loop height variations of bond wires under different heating currents are experimentally measured, based on which the finite element analysis (FEA) simulation is calibrated and verified to reveal the actual thermo-mechanical stress. In this way, the usefulness of our proposed method is verified by comparing its simulation results with those from the multi-physics fields FEA method. Finally, the relationship between the bonding angle and the plastic strain at the heel of bond wires is established. This study would provide new perspectives into further research on thermo-mechanical fatigue analysis and optimal design of bond wires in power modules.