RF Performance Benchmarking of TSV Integrated Surface Electrode Ion Trap for Quantum Computing

Abstract

Surface electrode ion trap is highly promising for practical quantum computing due to its superior controllability on the trapped ions. With advanced microfabrication techniques, silicon has been developed as an ion trap substrate for delicate surface electrodes design and monolithic electro-optical components integration. However, the high RF loss of silicon hinders the possible large-scale implementation. In this work, we demonstrate a through silicon via (TSV) integrated ion trap, which has low RF loss due to the elimination of wire bonding (WB) pads on the surface and the miniaturization of form factor. We also fabricate two types of conventional WB traps with or without a grounding screen layer. The RF performances of different ion traps are tested and compared, in terms of on-chip S-parameter, postpackaging resonance, and resulting power loss. The results show that the TSV trap has low S21 (~0.2 dB at 50 MHz), high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> factor (~22), and low power loss (0.26 W) compared to WB traps. In addition, 3-D finite element modeling (FEM) is employed for electric field visualization and RF loss analysis of different traps. The extracted results from the modeling show a decent agreement with the measurements. In addition to various RF tests, the design, fabrication, and ion trapping operation of different ion traps are presented. This work provides insights into RF loss of ion trapping devices and offers a new solution for RF loss reduction.