(Invited) 3D Integration of Surface Electrode Ion-Trap on Silicon and Glass Substrates for Quantum Information Processing

Abstract

Surface electrode ion trap is a promising candidate for quantum information processing (QIP), due to its feasibilities towards large-scale fabrication. There are several important considerations for the realization of surface ion trap including choices of substrate and interconnections. In this paper, surface electrode ion traps on different substrates (e.g., high-resistivity silicon, silicon with ground plane and glass) are fabricated, assembled and tested. To simultaneously leverage the established fabrication technique of silicon and superior insulation property of glass, we further demonstrate a novel ion trap design with heterogenous integration of silicon and glass, acting respectively as ion trap and interposer substrates. The vertical connection between the silicon ion trap and the glass interposer is achieved by through silicon via (TSV) and micro bump. This combination demonstrates promising RF and trapping properties.Standard back end of line CMOS process is used for the fabrication of ion traps on both silicon and glass substrates. With 12-inch silicon/glass wafers, ~2,000 traps with different design dimensions can be fabricated simultaneously. For ion trap on high-resistivity silicon substrate (HR trap, Fig. 1(a)), lithography-defined electroplating of 3.7 µm Cu with Au finish is conducted on top of 3 µm patterned SiO2 layer. For ion trap on silicon with grounding plane (GND trap, Fig. 1(b)), 1 µm Cu damascene process is used to form the meshed grounding plane that shields silicon substrate from RF signal penetration. For ion trap on glass substrate (glass trap, Fig. 1(c)), Cu and Au can be directly electroplated onto glass substrate after adhesion and seed layers deposition. To evaluate the RF performance of various traps, S parameter measurement and resonator test are conducted. Glass trap features extremely low RF loss as compared to silicon counterparts.Heterogenous integration of silicon ion trap and glass interposer with TSV interconnections (TSV trap, Fig. 1(d)) is thus proposed, in which the possibility of integration with electronics (DACs) components is preserved on the silicon ion trap chip, whereas the RF performance of the entire device can be guaranteed by the glass interposer. As shown in Fig. 1(e) and (f), integrated photonics passive components such as grating couplers can be implemented into the silicon trap chip for ion addressing with laser. Additional grounding layer with designed openings on top of grating couplers is introduced to further minimize RF loss. 88Sr+ ions are successfully trapped on both glass and TSV traps.In summary, this work discusses the performance of ion traps on various substrates and demonstrates the silicon-glass integrated system to enable the scalability of surface electrode ion trap. The work was supported by A*STAR Quantum Technology for Engineering (A1685b0005). Figure 1