Wire Bond Research Articles

Enhancement of turn-off gate voltage waveform change by digital gate control for bond wire lift-off detection in IGBT module

The bond wire lift-off is the one of main failures for insulated gate bipolar transistors (IGBT) power modules. The wire lift-off increases parasitic inductance LeE in the module and the gate voltage Vge waveform is modulated by LeE·dIe/dt. Therefore, the Vge waveform has the potential for an indicator of condition monitoring. The Digital gate control (DGC) can control switching behavior precisely for low-loss and low-noise switching. It is also effective for sensitivity enhancement of Vge waveform changed by the wire lift-off. This paper reports how the DGC 2-step vector control (2-sVC) can improve the wire lift-off failure detection sensitivity by Vge waveform. The experiment results showed that the Vge spike was generated by LeE·dIe/dt at the turn-off switching and the spike generation timing depended on the wire number. The DGC obtained the larger timing-shift Δtwire and the amplitude ΔVge-surge than those at the conventional gate control. In addition, the best vector condition improved the trade-off between turn-off loss and collector voltage overshoot compared with the conventional gate control. From these results, the DGC is effective to enhance the sensitivity of bond wire lift-off detection by Vge waveform maintaining the best switching performance.

New model of crack propagation of aluminium wire bonds in IGBT power modules under low temperature variations

In this paper, a new model for wirebond degradation during power cycling in IGBT power module is proposed. This model is based on experimental crack propagation analyses and on a plastic strain empirical law. For the experiments, two power cycling tests in switching mode under high voltage were carried out respectively with junction temperature swings of ∆ Tj=30°C and 40°C at a minimal temperature of Tj,min=55°C. The DUTs and the test conditions were chosen so that only degradations of chip top-side interconnections could occur. The on-state voltage (VCE) was measured online during the tests as an indicator of wire and metallization degradations, moreover, the samples were removed at different aging stages. The removed samples were cross-sectioned in order to observe the crack propagation evolution with cycling. Concerning the plastic strain law, we used results from literature giving the evolution of the plastic strain variation (∆εpl) with bond-wire contact crack growth. As results, this new lifetime prediction model based on a modified Paris's law for aluminium wire bonds fatigue of IGBTs shows a good fitting of the test results and is it can be used to predict the lifetime under other load conditions. Finally, the lifetime of tested IGBT modules are estimated and used to verify the effectiveness of the proposed model.

Sub-kHz-Linewidth External-Cavity Laser (ECL) With Si3N4 Resonator Used as a Tunable Pump for a Kerr Frequency Comb

Combining optical gain in direct-bandgap III-V materials with tunable optical feedback offered by advanced photonic integrated circuits is key to chip-scale external-cavity lasers (ECL), offering wideband tunability along with low optical linewidths. External feedback circuits can be efficiently implemented using low-loss silicon nitride (Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ) waveguides, which do not suffer from two-photon absorption and can thus handle much higher power levels than conventional silicon photonics. However, co-integrating III-V-based gain elements with tunable external feedback circuits in chip-scale modules still represents a challenge, requiring either technologically demanding heterogeneous integration techniques or costly high-precision multi-chip assembly, often based on active alignment. In this work, we demonstrate Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> -based hybrid integrated ECL that exploit 3D-printed structures such as intra-cavity photonic wire bonds and facet-attached microlenses for low-loss optical coupling with relaxed alignment tolerances, thereby overcoming the need for active alignment while maintaining the full flexibility of multi-chip integration techniques. In a proof-of-concept experiment, we demonstrate an ECL offering a 90 nm tuning range (1480 nm–1570 nm) with on-chip output powers above 12 dBm and side-mode suppression ratios of up to 59 dB in the center of the tuning range. We achieve an intrinsic linewidth of 979 Hz, which is among the lowest values reported for comparable feedback architectures. The optical loss of the intra-cavity photonic wire bond between the III-V gain element and the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> -based tunable feedback circuit amounts to approximately (1.6 ± 0.2) dB. We use the ECL as a tunable pump laser to generate a dissipative Kerr soliton frequency comb. To the best of our knowledge, our experiments represent the first demonstration of a single-soliton Kerr comb generated with a pump that is derived from a hybrid ECL.

Load Current Injection Modes Affected Power Cycling Lifetime and Failure Mechanism of IGBTs

In this paper, the influence of load current injection modes (saturation mode and threshold mode), at standard DC power cycling, on the failure mechanism and lifetime of IGBTs is presented. 6 groups of power cycling tests, at almost the same test conditions, with 2 different current injection modes and 2 different packages are performed. The failure mode after power cycling is confirmed by on-line monitored electrical and thermal parameters (forward voltage drop <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> and thermal resistance <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">thjs</sub> ) and further by SAM (Scanning Acoustic Micrography) pictures. Failure mechanism is then analyzed and the power cycling lifetime is compared and explained, with the help of finite element simulations. All results show that the threshold load current injection mode, with the gate and collector shorted, in power cycling can indeed reduce the load current to a large extent for the desired junction temperature swing. However, the power cycling lifetime and failure mechanism are changed, especially for devices with bond wire failure. It is not recommended for power cycling lifetime evaluation.

A Universal Scaling Formulation of the Generalized Peck’s Equation for Corrosion Limited Lifetime in Self-Heated ICs

Since the early 1980s, the highly accelerated stress test in conjunction with conventional Temperature-Humidity-Bias testing has been the industry-standard method for interpreting relative humidity (RH) and temperature (T) dependent failure modes in non-hermetically packaged ICs, solar modules, and other electronic components. In recent years, however, testing requirements based on JEDEC standards and the corresponding lifetime extrapolation to end-use conditions using Peck’s equation have been criticized as overly conservative for modern self-heated logic/power ICs. In practice, the self-heated ICs correlate RH, and T in a way that is not explicitly accounted for by Peck’s equation. In this study, we investigate the IC lifetime due to electrochemical failures – Cu-Al bond wire corrosion – by considering the effects of ambient RH, T, duty cycle, and self-heating temperature rise using an integrated self-consistent finite element-based Multiphysics model and propose a generalized Peck’s equation for self-heated ICs. Our study reveals how the asymmetry between On and Off-state heating leads to dramatic suppression of the effective RH experienced by an integrated circuit and, most importantly, identifies that the corrosion of Cu-Al bond wire occurs in spikes during the on-off transition when both RH and T are high. The generalized Peck’s equation also predicts an elegant scaling relationship among the fundamental variables associated with a self-heated IC lifetime. The prediction is validated by experimental lifetime data from self-heated IC published in the literature. The experimental validation of the physics-informed generalized Peck’s equation suggests the possibility of more accurate (and optimistic) lifetime predictions of modern ICs and solar modules.

In Situ Diagnosis for IGBT Chip Failure in Multichip IGBT Modules Based on a Newly Defined Characteristic Parameter Low-Sensitive to Operation Conditions

To achieve the desired current capability, insulated gate bipolar transistor (IGBT) modules are normally composed of parallel chips. The bond wires fatigue on a certain chip will gradually cause the performance of the power module to degrade, and eventually lead to an unexpected catastrophic failure of the entire system. Therefore, this paper proposes an in-situ diagnosis method for bond wires fatigue in multichip IGBT modules based on a newly defined characteristic parameter. By sensitivity analysis, horizontal comparison and experimental test, the parameter was proven to have the advantages of being safe, low-sensitive to operation conditions and easy to extract. Correspondingly, the online monitoring circuit was designed on the basis of the voltage clamping technology, and further applied on an inverter prototype with 100 A peak current and 10 kHz switching frequency. The results showed that although with large change of junction temperature and load current, the proposed method can accurately diagnose IGBT chip failure by the sudden increase in the amplitude of the parameter. Moreover, the monitoring circuit can be both plug-and-play in the existing inverters and integrated in the gate drive circuit owing to the compact design, which is expected to avoid catastrophic failures of the inverter in field application.

A Lightweight Method for Detecting IC Wire Bonding Defects in X-ray Images.

Integrated circuit (IC) X-ray wire bonding image inspections are crucial for ensuring the quality of packaged products. However, detecting defects in IC chips can be challenging due to the slow defect detection speed and the high energy consumption of the available models. In this paper, we propose a new convolutional neural network (CNN)-based framework for detecting wire bonding defects in IC chip images. This framework incorporates a Spatial Convolution Attention (SCA) module to integrate multi-scale features and assign adaptive weights to each feature source. We also designed a lightweight network, called the Light and Mobile Network (LMNet), using the SCA module to enhance the framework's practicality in the industry. The experimental results demonstrate that the LMNet achieves a satisfactory balance between performance and consumption. Specifically, the network achieved a mean average precision (mAP50) of 99.2, with 1.5 giga floating-point operations (GFLOPs) and 108.7 frames per second (FPS), in wire bonding defect detection.

Surface-Mount Zero-Ohm Jumper Resistor Characterization in High-Speed Controlled Impedance Transmission Lines.

Zero-ohm resistors, also known as jumpers, are commonly used in early radio frequency (RF) prototypes as they can help engineers identify the most optimal engineering solution for their system or create application-specific hardware configurations in products. One of the key considerations when using zero-ohm jumpers in RF circuits is the potential for signal loss and interference. Every circuit connection creates a small amount of resistance and impedance, eventually adding up over long distances or in complex circuits. This paper proposes a quantitative characterization summary of standard 0201-, 0402-, 0603-, and 0805-size surface-mount package jumpers, as well as lead-free and lead solder wires, in high-frequency applications by means of time domain reflectometry (TDR) and S-parameter measurements. The typical offset from the target 50 Ω impedance was measured to be around 3 Ω, or 5.8% relative to the measured reference value. According to S-parameter measurement results, no visible impact on attenuation was spotted up to 5 GHz compared to the reference S21 curve.

Inkjet-printed electrical interconnects for high resolution integrated circuit diagnostics

As semiconductors continue to shrink in size and become more three-dimensional in shape, the size of defects that can induce a failure also reduces, pushing the need for better fault isolation. The resolving capability of microscopes used in failure analysis (FA) is frequently limited by how close the microscope can be brought to the circuit under test. Accessibility is often restricted by the presence of probe needles or wire bonds that are needed to power up the device during the measurement. Here, I describe a robust, rapid and cost-effective method to overcome the contacting bottleneck by re-routing the probe pads with a low-profile redistribution layer, realized by conductive inkjet printing. I demonstrate that the method enables analytical FA with high spatial resolution on a backside power delivery network structure in combination with the optical beam induced resistance change (OBIRCH) technique. Electrical and structural characterization of the printing process are also reported.

Investigation of CuAl IMCs Corrosion in Chloride Environment and its Prevention Strategy

Abstract In most current wire-bonding applications, electrical interconnection is accomplished by fine Cu wires bonded to Al bonding pads microfabricated on an IC chip and external contact pins of the PCB board. Corrosion-related failure defects between the Cu wire and Al bond pad have been an ongoing un-trackable reliability issue plaguing the IC packaging industry for the past ten years, despite approaching ppb levels. Most prior studies hypothesized that intermetallic compounds (IMCs) like Cu9Al4, and CuAl2 were responsible for the observed acute wire-bond lift-off corrosion defects. Further studies sought to quantify the rates of corrosion of these IMCs and explore the effects of mitigation efforts of adding Pd, relevant to Pd-coated Cu wire-bonding. However, utilizing a novel real-time corrosion screening approach, we previously established that peripheral bimetallic contact between Cu ball-bonds and Al bond pads also plays a substantial role in the aggressive Al pad corrosion, induced by chloride ion penetration, which often leads to device failure. In this work, we further explored the role of IMCs corrosion in wire-bond lift-off failure utilizing fundamental electrochemical studies to quantify rates of galvanic-induced corrosion of IMCs within the broader context of an interconnected stack of Al bond pad, Cu-Al IMCs and Cu bonding wire. We also explored the use of a corrosion inhibitor to suppress the galvanic corrosion currents of Al bond pad, and Al-rich IMCs when electrically connected to Cu wire or Cu-rich IMCs.

Insulated, Passivated &amp; Adhesively-Promoted Bond Wire Using All-in-One Al2O3 Coating

Insulated, Passivated &amp; Adhesively-Promoted Bond Wire Using All-in-One Al2O3 Coating

Digital Twins and Smart Manufacturing for Wire Bonding

Low cost, excellent flexibility, and high yield rate have long been the drivers of wire bonding technology. In the past decade, advancements in wire bonding technology have significantly improved wire bond reliability and strengthened the adoption of the technology while maintaining its competitive advantage. Digital twins of wire bonding can now simulate and optimize 3D wire loop shapes to facilitate design-for-manufacturing (DFM), increase design flexibility, reduce product development time, and improve overall package yields. In particular, the benefits of digital twins have been realized in system-in-package (SiPs), large stack-die memory applications, and complex high pin count packages with multiple looping tiers. With increasing package complexity and modular package configurations, the need for smarter functionalities is imperative. More recently, technological developments in wire bonding have been targeted toward furthering design, quality, and time-to-market (TTM) from an Industry 4.0 smart manufacturing perspective. In this paper, we will introduce new digital twin simulation techniques to detect potential interference between wire bond capillaries and wire loops, various dies, passive components, and other structures within the package. These advanced capabilities are demonstrated on a real application and shown to help in the detection of design issues early in the product cycle and aid in the selection of capillary, wire, as well as optimization of the package layout. All these factors significantly improve the overall TTM of semiconductor packages. Technologies that provide improvements via autonomous monitoring and optimization are also strongly desired. We will also explore new on-bonder process monitoring capabilities to detect wire sway such that wire shorts and resultant yield losses can be minimized. Additionally, vision-guided enhancements to on-bonder loop height monitoring capabilities will also be discussed. These new advancements significantly improve production quality and yield, paving the way for smarter factories

New Packaging Technology for 2-dimensional VCSEL Arrays and Their Electro-Optical Performance and Applications

At IMAPS2021, we reported on 1-dimensional VCSEL arrays and the packaging technology developed for these arrays, but this time we present the manufacturing workflow and look at the challenges presented by the packaging of special long-wavelength 2-dimensional vertical-cavity surface-emitting laser (VCSEL) arrays in various dimensions. We will show that available packaging technologies for epoxy application by silk screening, die- and wire bonding can be adapted for the unique properties of the 2D VCSEL arrays, delivering high accuracy for production with great overall yield. Proof of the excellent reliability and lifetime will be given through mechanical and electro-optical testing results. The technologies developed for 2D laser arrays will enable new devices for various new applications like high channel count interconnects for data communication and high power VCSEL solutions for 3D sensing. The perfected wire bonding process secured a homogeneous monometallic structure of the wire bonds, a reduced, well defined bond loop height, with sufficient clearance of the bonding wire above the VCSEL surface. Properly set-up manufacturing procedures for the packaging of the VCSEL arrays are necessary to achieve high performance and reliability of the products presented. Processing of large 2D-VCSEL arrays will be part of the paper. 2D arrays have enabled VCSEL technologies to address a wide range of new laser-based sensing applications. VCSEL products vary from laser chips with only a few emitters for proximity sensors up to several thousands of emitters for LiDAR systems. Applications include systems for the automotive, industrial, medical and consumer markets. There is a strong and growing market opportunity for long wavelengths VCSELs, e.g. based on InP material enabling single mode and multi-mode 2D-VCSEL arrays from 1.3 to beyond 2 µm. For 3D sensing systems and free-space optical communication, long wavelength 2D-VCSEL arrays offer improved eye safety and further benefits. The long wavelength VCSELs discussed in this paper can be deployed in a wide range of sensing and optical communication applications.

An Organic Package Designer’s Guide to Transitioning to FOWLP and 2.5D Design

Many package designers have many years of hands-on experience designing organic FR4/HDI build-up BGA/LGA substrates. We’ve memorized the design guidelines and the substrate fabrication is well understood. We know how to wield our design tools like precision scalpels to get the design completed on-time, on-specification and on budget. Whether it’s flipchip attach, wire bond or a stacked die combo the design methodology is well understood. Then management mentions that the next generation of designs are going to be “heterogeneously integrated”, utilizing new integration platforms such as RDL-based fan-out wafer level and/or interposers. Suddenly, people start mentioning things like “Assembly Design Kits”, “Stream-out”, “sign-off using PDK’s”, multi-pass degassing, seal rings, assembly LVS and HBM stack routing. The suggestion is made that new design tools might be needed – semiconductor P&amp;R tools that only work on Linux and are all TCL/TK script driven. We start doing some research online and attend a conference or two and listen to some of the EDA tool vendors and you could easily arrive at a point where you start to think, “Am I obsolete? Do I really need to learn to use silicon P&amp;R tools? What is “assembly LVS”, multiple-pass degassing and why do my metal planes need to be hatched and offset?” For many of us, the shift in technology can be overwhelming. Do not despair; yes, there is new terminology to understand and many new design techniques to be understood and mastered, as well as a completely new design process and flow. The good news is that this can all be overcome without having to learn silicon P&amp;R design tools. This paper will discuss real-world experiences of organic package substrate designers who have transitioned and mastered RDL-based FOWLP and 2.5D silicon and organic interposer design, while still using (and preserving) the majority of their existing packaged design tools and skills.

High Robustness of Coated-Ag Wire Bonding

Formation of free air ball (FAB) within the range of certain processing parameters leads to excellent bondability (distributed intermetallic coverage (IMC) at the center and periphery of the bonded ball interface, bonded ball concentricity, etc.) on bonding to aluminum (Al) bond pad and Au/Ag plated surfaces. The wire revealed zero stoppage and 0.8M bond touchdowns when tested under laboratory conditions. Thermal aging of bonded interface showed absence of Kirkendall voids until 192h at 250°C where Al diffuses into Ag bonded ball up to a depth of 5.3µm, consuming the complete Al bond pad and thus transforming into silver-aluminide containing 5 to 12wt% of Al and rest silver (Ag). Traces of coated gold (Au) and alloyed palladium (Pd) are noticed at the bond interface.

Algorithm for Ultrasonic Wire Bond Outlier Classification

Wedge bonders use ultrasonic energy to bond metal wires onto metal substrates in a process that takes milliseconds. In high-volume production, failures cause downtime and costs. On-line monitoring systems are used to reduce the failures and determine the root cause. We developed and tested an algorithm to classify outliers in ultrasonic wire bond production. The algorithm is used in large wire wedge bonders to measure and analyze process signals and detect and classify bond outliers. It helps bonder operators, production supervisors and process engineers to detect process deviations and fix the underlying root causes. The algorithm measures bond signals, such as deformation, ultrasonic current, and ultrasonic frequency. Bonds are automatically divided into subgroups based on bond order and process parameters, and the signals within a subgroup are then normalized. For outlier classification, the features are extracted from the normalized signals and combined into failure class values. The failure classes such as contamination, no wire, high deformation, misaligned wire, and unstable substrate, are calculated independently. We measured the detection rates for large wire aluminum bond failure classes and demonstrate how the algorithm calculates failure class values from the signals. Additionally, we show how new signal features and failure classes can be defined to detect production-specific or rare failure classes.

Metal Oxide Removal Using Atmospheric Pressure Plasma Technology for Electronic Applications

Copper is one of the most commonly used metals in the electronics industry. For example, it is extensively used as a lead frame material in integrated circuit packaging due to its superior thermal and electrical conductivity and low production cost. However, the formation of a native oxide on the surface along with the presence of organic contaminants hinder wire bond strength. The work presented here will focus on a novel approach to remove copper and other oxide layers using a nitrogen/hydrogen (95%/5%) gas plasma chemistry that does not require a vacuum environment. The processes are run at temperature conditions lower than 200°C, and at speed up to 150 mm/s which make the technology attractive for industrial upscaling. Results from the elemental analysis using scanning electron microscopy (EDS-SEM) of the plasma-treated versus as-received copper surfaces will be presented. Also, a brief analysis of the gas plasma-surface interactions, process parameters leading to oxide reduction of various metals (Cu, Sn) and equipment details will be discussed. Aside from improving wire bond strength to lead frames and pads, plasmas can be used to improve die attachment to various metal solder materials for flip chip and other electronic applications.

A Comprehensive Evaluation of Al Heavy Wire Bonding and Ribbon Bonding Application in high power WBG Power Modules

Targeting at a comprehensive Multiphysics evaluation for Al wire and ribbon bonding technologies for WBG power module, this paper investigates and compares the stray inductance, heat dissipation and fatigue life between these two bonding schemes in an XHP packaging designed in house. During calculation, it was tried to keep equivalent volume for the Al ribbon when substituting local Al wires for fair comparison. Results of stray inductance show extremely limit bonding-type dependence in ranges from 1 kHz to 10 MHz, and further expanding ribbon size to varied levels still presents negligible impact. The two bonding technologies do not prove their capability in sharing either static or transient thermal loads when the baseplate bottom is efficiently liquid cooled. Detailed study confirms that heat dissipates dominantly in vertical direction to the Cu baseplate rather than through Al bonds. Ultimately, the only noticeable benefit of Al ribbon in our multiscale analysis is its improved reliability during temperature cycling, with data supporting a 2.17× times longer lifetime of Al ribbon when comparing to its Al wire counterpart.

Optimization of the Copper Microstructure to Improve Copper-to-Copper Direct Bonding

Advanced packaging solutions and heterogeneous integration are key technologies to enable devices with improved operating characteristics, including higher performance, increasing power efficiency, and decreasing form factor. Packages with high interconnect densities are required to efficiently combine, e.g., processing and memory units but impose restrictions to the pitch of the interconnects. Conventional technologies, including wire bonds and flip chip bonds are limited to larger pitches and, therefore, not suitable to meet the requirements of upcoming packaging technologies with respect to interconnect densities. Direct copper-to-copper interconnects are supposed to allow such small pitches of 10 µm or even below. However, formation of such bonds usually requires high temperatures and pressures. Temperature-sensitive devices like DRAM components restrict the maximum temperature that can be applied to the package. Thus, copper material is required, which allows bond formation at relatively low temperatures. In this context, hybrid bonding processes were discussed that involve initial bond formation via the usually oxide-based dielectric at room temperature followed by copper-to-copper bonding at elevated temperatures. The copper material is usually prepared by electrolytic deposition and the properties of the respective deposits may be modified by properly designed organic additives as well as process parameters. Strong bond formation of the copper should be obtained upon grain growth over the interface of the two deposits, which are brought into contact during the bonding step. In order to facilitate such growth at relatively low temperatures, suitable microstructures need to be prepared. Ideally, morphologies should be chosen in a way that they can be maintained throughout all process steps after the electrolytic deposition but, at the same time, allow grain growth over the interface during copper-to-copper bonding. Various strategies to enable improved seamless grain growth but maintain a metastable microstructure throughout the preceding process steps and the corresponding unique copper microstructures will be compared. In this context, different electrolytic copper deposition processes, the resulting microstructures, as well as their respective advantages and challenges with regards to copper-to-copper bond formation will be discussed.

Printed Microstrip Interconnects for Improved RF Performance in mm-Wave Packaging

Printed microstrip interconnects are gaining attention as designers seek a more-compact, lower-loss scheme to replace wire bonds. Aerosol Jet® printed interconnects have the potential to lower insertion losses by creating conductors with arbitrary geometries and zero loop height. Printed dielectric and conductor materials typically have inferior electrical properties compared to bulk-deposited materials. There is a question whether these properties will produce unacceptable S21 losses in printed interconnects. This work presents calculations of the effect of the printed material’s properties on S21. HFSS modeling from 0.1 to 100 GHz was conducted on two representative interconnect structures. A trench in an RF substrate filled with dielectric and a dielectric ramp from a substrate up to a GaAs die. The microstrip (or transmission) line over a filled trench represents the filled region around a die that sits down in a “pocket” in the dielectric and contacts the ground plane. Conductors modeled include a pure copper reference along with conductors with four and ten times the resistivity of bulk silver. The dielectric constant of the insulator varied from 2.8 to 4.3 and the loss tangent varied from 0.004 to 0.04. For simplicity, an unpatterned GaAs die was used in place of an RF IC. The work focuses on estimating any degradations in performance of an ideal reference circuit caused by the material properties of real printed materials. Also presented are the dielectric properties of our current materials along with properties of candidate materials that have better thermo-mechanical properties (shrink, CTE, Tg…).