Memory Window Width Research Articles

Fabrication and characterization of metal-ferroelectric-insulator-Si diodes and transistors with different HfSiON buffer layer thickness

Metal-ferroelectric-insulator-Si (MFIS) structures using HfSiON as buffer layers were fabricated, and the impact of buffer layer thickness on the electrical properties of the MFIS devices was investigated. HfSiON films with thickness ranging from 1 to 4 nm were deposited by electron beam evaporation, which exhibited much reduced leakage current when compared to that of SiO2 with the same equivalent oxide thickness. From the viewpoint of polarization and charge injection, the flatband voltage and memory window width dependent on the sweeping voltages were discussed for the MFIS diodes with 1-, 2-, and 4-nm-thick HfSiON buffer layers. Small leakage current as well as excellent long-term data retention characteristics were found for all of these samples. It was also found that MFIS diodes with 2-nm-thick HfSiON buffer layer have the largest memory window width. Ferroelectric-gate transistors fabricated with a Pt/SBT(300nm)/HfSiON (2 nm)/Si gate structure showed a memory window of 0.8 V and a high drain current on/off ratio of 108 for the gate voltage sweep between +4 and −4 V. All of these excellent electrical properties proved that HfSiON acts as an excellent barrier for suppressing both leakage current and atomic interdiffusion.

CHARACTERIZATION OF METAL-FERROELECTRIC-SEMICONDUCTOR STRUCTURE USING FERROELECTRIC POLYMER POLYVINYLIDENE FLUORIDE-TRIFLUOROETHYLENE (PVDF-TrFE) (51/49)

ABSTRACT In this work, we fabricated metal-ferroelectric-semiconductor (MFS) diodes with polyvinylidene fluoride-trifluoroethylene (PVDF-TrFE) (51/49) thin films for application to one transistor-type (1T-type) ferroelectric random access memories (FeRAMs). The thin films, with various thicknesses, were prepared on a silicon substrate by using a spin-coating method. The β-phase crystallinity and the grain size of the PVDF-TrFE increased as the film-thickness increased. Typical ferroelectric hysteresis loops were obtained from the capacitance-voltage (C-V) curves. These loops might be considered to be due to the ferroelectric nature of the PVDF-TrFE films. The values of the memory window width for 50-nm-, 150-nm-, and 350-nm-thick PVDF-TrFE films were about 1.4, 2.0, and 3.5 V for a bias sweeping from −5 V to 5 V, respectively. The values of the leakage current density, at a sweeping range of ± 5 V, were about 2.7 × 10−5 A/cm2, 1.1 × 10−5 A/cm2, and 5.6× 10−6 A/cm2 for 50-nm-, 150-nm-, and 350-nm-thick films, respectively. These results are useful and promising for realizing 1T-type FeRAMs operating at a low voltage.

ENHANCEMENT OF MEMORY RETENTION TIME OF MFIS STRUCTURE WITH SBT FERROELECTRIC AND SiO2 BUFFER LAYERS TREATED BY NITROGEN RADICAL IRRADIATION

ABSTRACT Nitrogen radical irradiation has been used to improve the retention memory characteristic of Pt/SrBi2Ta2O9(SBT)/SiO2/n-Si metal–ferroelectric–insulator–semiconductor (MFIS) structures. It is demonstrated leakage currents through buffer and ferroelectric layers have decreased due to improvements of electronic property by the irradiation treatment. Furthermore, C-V characteristics also show wide memory window and steep slope in depletion region corresponding to good interface layers and minimized diffusion between layers. Nitrogen incorporated in surface layers of SiO2 and SBT has been confirmed by X-ray Photoelectron Spectroscopy(XPS). Ultraviolet Photoyield Spectroscopy(UV-PYS) measurements show Fermi level energy and band gap of SBT surface layer are modified and depend on radiation time. Surface morphology of SBT thin films with various treatment periods were investigated by SEM and AFM images. The retention time of capacitor in ON and OFF states of MFIS structures is longer than 2 weeks.

Floating nanodot gate memory fabrication with biomineralized nanodot as charge storage node

We have demonstrated floating nanodot gate memory (FNGM) fabrication by utilizing uniform biomineralized cobalt oxide (Co3O4) nanodots (Co-BNDs) which are biochemically synthesized in the vacant cavity of supramolecular protein, ferritin. High-density Co-BND array (>6.5×1011cm−2) formed on Si substrate with 3-nm-thick tunnel SiO2 is embedded in metal-oxide-semiconductor (MOS) stacked structure and used as the floating gate of FNGM. Fabricated Co-BND MOS capacitors and metal-oxide-semiconductor field effect transistors show the hysteresis loop due to the electron and hole confinement in the embedded Co-BND. Fabricated MOS memories show wide memory window size of 3–4V under 10V operation, good charge retention characteristics until 104s after charge programming, and stress endurance until 105 write/erase operation. Observed charge injection thresholds suggest that charge injection through the direct tunneling from Si to the energy levels in the conduction and valence bands of Co3O4 and long charge retention characteristics implies prompt charge confinement to the deeper energy level of metal Co which is formed during the annealing in the device processing.

Fabrication and characterization of Au/SBT/LZO/Si MFIS structure

Ferroelectric SrBi2Ta2O9 (SBT) films on a p-type Si (100) wafer with a LaZrOx (LZO) buffer layer have been fabricated to form a metal-ferroelectric-insulator–semiconductor (MFIS) structure. The LZO thin film and SBT films were deposited by using a sol–gel method. The equivalent oxide thickness (EOT) value of the LZO thin film was about 8.83 nm. Also, the leakage current density of the LZO thin film is about 3.3 × 10−5 A/cm2 at bias sweeping voltage of ±5 V. SBT films were crystallized in polycrystalline phase with highly preferred (115) orientation. Also, the intensity of each pick slightly increased as thickness of SBT films increased. The C–V characteristics of Au/SBT/LZO/Si structure showed clockwise hysteresis loop. The memory window width increased as the thickness of SBT films increased. The leakage current density of Au/SBT/LZO/Si structure decreased as thickness of SBT films increased.

Electrical and Memory Properties of Si3N4 MIS Structures with Embedded Si Nanocrystals

Memory structures with an embedded sheet of separated Si nanocrystals were prepared by low pressure chemical vapour deposition using a Si3N4 control layer and different Si2O2 or Si3N4 tunnel layers. It was obtained that Si nanocrystals improve the charging behaviour of the MNOS structures. Memory window width of 1.3 V and 2.0 V were obtained for pulse amplitudes of +/-9 V and +/-10 V, 100 ms, respectively. The extrapolated memory window after 10 years is about 15% of its initial value.

Ferroelectric properties of SrBi2Ta2O9 thin films on Si (100) with a LaZrO x buffer layer

To obtain a metal–ferroelectric–insulator–semiconductor (MFIS) structure, we fabricated ferroelectric SrBi2Ta2O9 (SBT) film on a p-type Si (100) wafer with a LaZrOx (LZO) buffer layer by means of a sol–gel technique. The sol–gel deposited LZO film according to the different annealing temperatures had a good surface morphology even though the crystalline phase was not an amorphous phase. In particular, the root-mean-squared (RMS) surface roughness of the 750-°C-annealed LZO film was about 0.365 nm and its leakage current density was about 8.2 × 10−7 A/cm2 at 10 V. A Au/SBT/LZO/Si structure with different SBT film was fabricated. The C–V characteristics of the Au/SBT/LZO/Si structure showed a clockwise hysteresis loop. The memory window width increased as the SBT film thickness increased. The 600-nm-thick SBT film was crystallized in a polycrystalline phase with a highly preferred (115) orientation. The memory window width of the 600-nm-thick SBT film was about 1.94 V at the bias sweep voltage ±9 V and the leakage current density was about 6.48 × 10−8 A/cm2 at 10 V.

Electrical Characteristics of Metal–Ferroelectric–Semiconductor Structures Based on Poly(vinylidene fluoride)

We prepared poly(vinylidene fluoride) (PVDF) films in the β phase by a sol–gel method using PVDF solutions with different weight fractions. The electrical properties of PVDF films were studied for the possibility of using them in one-transistor (1-T)-type ferroelectric random-access memories (FRAMs). In this research, the Au/PVDF/Si structure made from PVDF solution of 6 wt % concentration showed good ferroelectric and electrical properties. The memory window width and current density for the PVDF film from the 6 wt % PVDF solution were about 1.8 V and 10-6 A/cm2 for a bias voltage of 5 V, respectively. It is expected from these good ferroelectric properties that PVDF films will be suitable for low-cost 1-T-type FRAMs operating at a low voltage.

The Ferroelectricity and Electrical Properties of P(VDF-TrFE) Copolymer Film

Poly(vinylidene fluoride-trifluoroethylene)(P(VDF-TrFE)) copolymer thin films with a molar ratio of 75/25 have been studied to investigate their ferroelectricity. P(VDF-TrFE) solutions of 3, 7 and 10 wt% were fabricated on Si(100) substrates by using a spin-coating method. In order to achieve crystallization, we annealed the deposited films at 150 ◦C for one and half hours without any addional treatments, such as a heat-treatment, poling, or mechanical drawing. The thicknesses of the deposited films were 60, 170 and 400 nm for the 3, 7 and 10 wt% solutions, respectively. Hysteretic characteristics were observed in the capacitance-voltage (C-V) curves for Au/P(VDFTrFE)/Si diodes and may be considered to be due to the ferroelectric nature of the P(VDF-TrFE) films. The memory window width was measured at a low voltage below 1 V for a film coated with a 3 wt% solution. The memory window widths in this metal-ferroelectric-semiconductor (MFS) fabricated with 3, 7 and 10 wt% P(VDF-TrFE) solutions were about 1.2, 2.7 and 3.6 V for a bias sweep from –5 V to 5 V, respectively.

Electrical Properties of Metal-Ferroelectric-Semiconductor Structures Based on Ferroelectric Polyvinylidene Fluoride (PVDF)

A PVDF (polyvinylidene fluoride) thin film having a phase was prepared by using sol-gel method. The film’s properties were studied to evaluate the possibility of use in a ferroelectric random access memory. In order to characterize its electrical properties, we produced a MFS (metal-ferroelectric-semiconductor) structure by evaporation of Au electrodes. The C-V (capacitance-voltage) measurements revealed that the Au/PVDF/Si structure with a 7 wt% film had a memory window width of about 1.8 V for a bias voltage sweep of 4 V.

BLT/STA/Si Structure for MFIS in an NDRO-Type Ferroelectric Random Access Memory

Ferroelectric (Bi,La) 4 Ti 3 O 12 (BLT) thin films were prepared on a p-type Si (100) wafer with a SrTa 2 O 6 (STA) buffer layer for a metal-ferroelectric-insulator-silicon (MFIS) structure. The STA buffer layer was completely crystallized at the high temperature over 800°C. We observed that STA thin films fabricated at 900°C for 3 minutes in O 2 ambient had good insulating properties. Their EOT value was about 5.7 nm. Considering the distribution of the bias voltage on a series capacitor, the ferroelectric BLT and the dielectric STA, BLT thin films with a different thickness were formed on STA/Si structures and characterized by C-V measurement including memory windows. It was found that the memory window width was about 1.5 V for the ±5 V bias sweeping with the 600 nm thick BLT films on STA/Si structure. The leakage current density was about 1.0 × 10−7 A/cm 2 at 5 V. These results are useful and promise the realization of a MFIS structure with the BLT and a STA layer for non-destructive read-out (NDRO) type ferroelectric memories.

FABRICATION AND CHARACTERIZATION OF MFIS-FET USING Bi3.25La0.75Ti3O12/ZrO2/Si STRUCTURE

ABSTRACT A metal-ferroelectric-insulator-semiconductor structure (MFIS) has been fabricated by ZrO2and Bi3.25La0.75Ti3O12 as the buffer layer and ferroelectric film in forming MFIS diodes on Si(100) substrates, respectively. ZrO2 films were prepared by a sol-gel method. Then, they were carried out dry O2 annealing in a rapid thermal annealing (RTA) furnace at 700°C for 10 min. On the ZrO2/Si structures, Bi3.25La0.75Ti3O12 films were deposited by sol-gel method and they crystallized rapid thermal annealing in O2 atmosphere at 750°C for 30 min. They were characterized by X-ray diffraction analysis (XRD) and atomic force microscopy (AFM). The memory window width in capacitance-voltage(C-V) curve of the Au/BLT/ZrO2/Si diode was about 1.0 V for a voltage sweep of ± 4 V. Base on these results, we fabricated the MFIS-FET structure. The memory window width in drain current–gate voltage (ID–VG) curve of the MFIS-FET was about 0.7 V.

ELECTRICAL PROPERTIES OF Pt/BLT/HfSiON/Si STRUCTURE FOR 1T-TYPE FERROELECTRIC MEMORY

ABSTRACT Using HfSiON as a buffer layer, we fabricated metal-ferroelectric-insulator-semiconductor field-effect-transistor (MFIS FET). The HfSiON film was deposited in a high vacuum chamber with electron beam evaporation. A HfSiON film was amorphous even after annealing at 800°C in O2 atmosphere. MFIS diodes with a Pt/BLT((Bi,La)4Ti3O12)/HfSiON/Si structure showed hysteresis loop with a 0.5 V memory window when the voltage was swept between 5 V and −5 V. When the diode was biased in the hysteresis loop, the high and low capacitance values were kept at least for 24 hours. P-channel MFIS FET with a Pt/BLT((Bi,La)4Ti3O12)/HfSiON/Si structure showed the hysteretic Ids-Vg characteristic with 0.5 V memory window width, when a gate voltage was swept between 5 V and −5 V.

CHARACTERIZATION OF (Bi,Nd)4Ti3O12/HfO2/p-TYPE Si STRUCTURES FOR MFIS-FeRAM APPLICATION

ABSTRACT Metal-Ferroelectric-Insulator-Semiconductor (MFIS)-FET using (Bi, Nd)4Ti3O12 (BNT)/HfO2/p-type Si structure was fabricated and characterized. HfO2 and BNT thin films were formed by metalorganic chemical vapor deposition (MOCVD) and chemical solution deposition (CSD) method, respectively. The p-type Si substrate was used to take advantage of the large ON current of n-channel FET. The fabricated MFIS-FET showed a good ID-VD, characteristics. The ID-VG curve showed the memory window width of 0.8 V. The relation between the memory window and sweep voltage was investigated, and it appeared that the applied voltage influenced to both polarization switching and charge injection.

Optimum Ferroelectric Film Thickness in Metal–Ferroelectric–Insulator–Semiconductor Structures Composed of Pt, (Bi,La)4Ti3O12, HfO2, and Si

The optimum ferroelectric film thickness in metal–ferroelectric–insulator–semiconductor (MFIS) structures is investigated, in which 80- to 560-nm-thick (Bi,La)4Ti3O12 (BLT) films are deposited on HfO2 buffer layers using a sol–gel spin-coating method. It is found from electrical characteristics of MFIS diodes as well as MIS diodes that the HfO2 layers act as excellent barriers for suppressing both leakage current and atom interdiffusion when they are annealed in a rapid-thermal-annealing furnace at 900 °C for 1 min in O2 flow. In MFIS diodes, the memory window width in capacitance–voltage (C–V) characteristics is found to increase from 0.2 to 1.6 V, as ferroelectric film thickness increases from 80 to 560 nm. On the basis of these results, the relationships among memory window width, ferroelectric film thickness, and the optimum applied voltage are discussed. Finally, it is shown from the capacitance change measured over 24 h that data retention characteristics are excellent in samples with BLT films thicker than 240 nm.

Memory effects of carbon nanotubes as charge storage nodes for floating gate memory applications

A nonvolatile flash memory device has been fabricated using carbon nanotubes (CNTs) as a floating gate embedded in HfAlO (the atomic ratio of Hf∕Al is 1:2) high-k tunneling/control oxides and its memory effect has been observed. Capacitance-voltage (C-V) measurements illustrated a 400mV memory window during the double C-V sweep from 3 to −3V performed at room temperature and 1MHz. Further studies on their programming characteristics revealed that electron is difficult to be written into the CNTs and the memory effect of the structures is mainly due to the holes traps. The memory window width can remain nearly unchanged even after 104s stressing, indicating excellent long term charge retention characteristics. We therefore suggest that the CNTs embedded in HfAlO can be potentially applied to floating gate flash memory devices.

Self-aligned TiSi2∕Si heteronanocrystal nonvolatile memory

The titanium silicide/silicon (TiSi2∕Si) heteronanocrystals are fabricated on SiO2 thin films. The metal-oxide-semiconductor structure embedding the TiSi2∕Si heteronanocrystals shows superior performance over the Si dot device. The charge loss rate in the TiSi2∕Si heteronanocrystal device is 7.5 times less than that of the Si dot device. It is also found that the TiSi2∕Si heteronanocrystal device has wider memory window than the Si dot counterpart.

Five-day-long ferroelectric memory effect in Pt∕(Bi,La)4Ti3O12∕HfO2∕Si structures

In order to form metal–ferroelectric–semiconductor–insulator–semiconductor (MFIS) structures, hafnium oxide (HfO2) films were first deposited on Si(100) substrates at room temperature using an electron-beam evaporation method. Then, they were annealed in an O2 atmosphere at 800°C for 1min. No hysteretic characteristics were observed in the capacitance–voltage (C–V) measurement for the metal–insulator–semiconductor capacitors. On these films, lanthanum-substituted bismuth titanate [(Bi,La)4Ti3O12:BLT] films with 380nm in thickness were deposited by a sol–gel spin-coating method and annealed in an O2 atmosphere at 750°C for 30min. The MFIS sample showed the hysteretic C–V characteristics and the memory window width was about 0.9V for the voltage sweep of ±7V. Furthermore, the high and low capacitance values biased in the hysteresis loop were clearly distinguishable for over 5 days. The origin of the excellent data retention characteristics is discussed from a viewpoint of the transient current across the film.

Characteristics of Pt/Bi3.25La0.75Ti3O12/ZrO2/Si structures using ZrO2 as buffer layers for ferroelectric-gate field-effect transistors

We investigated the structural and electrical properties of Bi3.25La0.75Ti3O12 (BLT) films grown on Si covered with ZrO2 buffer layer. The BLT thin film and ZrO2 buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the metal–ferroelectric–insulator–semiconductor (MFIS) structure were investigated by varying thicknesses of the ZrO2 layer. The width of the memory window in the capacitance–voltage curves for the MFIS structure decreased with increasing thickness of the ZrO2 layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about 4 orders of magnitude after using ZrO2 buffer layer. Transmission electron microscopy shows no interdiffusion and reaction that was suppressed using the ZrO2 film as a buffer layer.

Fabrication and Characterization of (Bi,La)4Ti3O12 Films Using LaAlO3 Buffer Layers for MFIS Structures

We formed MFIS (metal-ferroelectric-insulator-semiconductor) diodes by depositing Bi3.35La0.75Ti3O12 ferroelectric films and LaAlO3 buffer layers on Si(100) substrates. LaAlO3 films were prepared by an MBD (molecular beam deposition) method, and they were subjected to ex situN2 annealing in RTA (rapid thermal annealing) furnace at 800°C for 1 min. On the optimized LaAlO3/Si structure, a BLT film with 480 nm in thickness was deposited by a sol-gel technique. The memory window width in C-V (capacitance-voltage) curve of the Pt/BLT/LaAlO3/Si diode was about 4.5 V for voltage sweep of ±10 V. It was also found that the retention time of this diode was longer than 5 days.