Wideband CMOS Low Noise Amplifier Research Articles

A K-/Ka-Band Broadband Low-Noise Amplifier Based on the Multiple Resonant Frequency Technique

A wideband CMOS low-noise amplifier (LNA) with multiple resonant frequencies is demonstrated in this article. A common source (CS) with inductive degeneration topology is widely employed in LNA circuit design to decouple the input impedance from the noise figure (NF). Since CS with inductive degeneration topology only achieves a single resonant frequency, it generally has narrow bandwidth performance. Through impedance transformation analysis of the matching circuit, a shunt resonator combined with inductive degeneration topology employed for input impedance transformation is carefully constructed to form multiple resonant frequencies. By placing resonant frequencies further apart from each other, impedance fluctuations within a wideband frequency range can be alleviated. In addition, the noise performance of this topology is the same as that of a conventional CS source-degenerated structure. The proposed LNA for the whole K/Ka Band is implemented in a commercial 65-nm CMOS process. It occupies 0.28 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Under a 1.0 V voltage supply, the LNA achieves 3-dB gain bandwidth of 28 GHz from 16.5 GHz to 44.5 GHz. Within the whole 3-dB bandwidth, the gain is larger than 15.5 dB, the NF is less than 4.8 dB with a minimal value of 2.72 dB, and the input 1-dB gain compression point (IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1<i>dB</i></sub> ) varies from −24 dBm to −12 dBm.

A Low Power Single Ended Inductorless Wideband CMOS LNA With Gm Enhancement and Noise Cancellation

This work proposes a low power single ended wideband CMOS low noise amplifier for low power short-range wireless communication based on IoT. The main novelty lies in significant improvement in bandwidth by using the inverter cell and in noise by noise cancellation topologies. By using active shunt-feedback architecture, the current of the feedback stage is reused on the forward path to improve the current efficiency of the LNA. The complementary characteristic leads to partial second-order distortion cancellation simultaneously. With TSMC 180 nm CMOS process, the proposed LNA presents maximum voltage gain of 15 dB, a minimum noise figure of 1.79 dB and an input 1 dB compression point of -24.65 dBm. It consumes 3 mW from 1.8 V dc supply and occupies a core area of 0.004 mm².

A 53–117 GHz LNA in 28-nm FDSOI CMOS

This letter presents the design of a wideband millimeter-wave (mm-wave) low-noise amplifier (LNA) in a 28-nm FDSOI CMOS technology. Having a total power consumption of 38.2 mW, the LNA provides gain over 12 dB from 53 to 117 GHz, and has a measured NF of 6 dB from 75 to 105 GHz. To the author’s best knowledge, the presented LNA achieves the lowest NF with widest bandwidth among previously presented wideband CMOS LNAs operating in the W-band.

A low-power, low-noise and high linearity 60 GHz wideband CMOS low-noise amplifier for wireless personal area network (WPAN) systems

A low power and low noise figure (NF) 60 GHz wideband low-noise amplifier (LNA) with excellent phase linearity for wireless personal local network (WPAN) systems using standard 90 nm CMOS technology is reported. To achieve sufficient power gain (S21) and reverse isolation (S12), the LNA comprises a common-source (CS) stage followed by a cascode stage and a CS stage. The LNA consumes 14.1 mW, achieving S11 better than ?10 dB for frequencies 55.1---59.5 GHz, S22 better than ?10 dB for frequencies 55.1---59.4 GHz, S12 better than ?42.6 dB for frequencies 50---64 GHz, and group delay variation smaller than ±13.25 ps for frequencies 50.4---63 GHz. Additionally, high and flat S21 of 9.9 ± 1.5 dB is achieved for frequencies 50.4---62.9 GHz, which means the corresponding 3-dB bandwidth is 12.5 GHz. Furthermore, the LNA achieves minimum NF of 3.88 dB at 55.5 GHz and NF of 4.73 ± 0.85 dB for frequencies 50---63.5 GHz, one of the best NF results ever reported for a 60 GHz CMOS LNA.

Study of Linearity and Power Consumption Requirements of CMOS Low Noise Amplifiers in Context of LTE Systems and Beyond

This paper presents a study of linearity in wideband CMOS low noise amplifiers (LNA) and its relationship to power consumption in context of Long Term Evolution (LTE) systems and its future developments. Using proposed figure of merit (FoM) to compare 35 state-of-the-art LNA circuits published over the last decade, the paper explores a dependence between amplifier performance (i.e., combined linearity, noise figure, and gain) and power consumption. In order to satisfy stringent linearity specifications for LTE standard (and its likely successors), the paper predicts that LNA FoM increase in the range of +0.2 dB/mW is expected and will inevitably translate into a significant increase in power consumption—a critical budget planning aspect for handheld devices, active antenna arrays, and base stations operating in small cells.

A compact wideband CMOS LNA with low power consumption

In this letter, a wideband low noise amplifier (LNA) operating at 1–5 GHz is proposed.The circuit is designed with a TSMC 0.18-μm RF CMOS process. To obtain high transconductance with low power consumption, two types of inverters are used. The proposed LNA is expected to reduce the size of chip about 70–80% by using only the single-spiral inductor. The measured voltage gain is 14.4–15.5 dB and noise figure (NF) is 4.3–5.0 dB from 1–5 GHz. The total power consumption of the proposed LNA is 9.8 mW from a 1.4 V supply voltage and chip area occupies only 0.5 × 0.5 mm2. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2360–2363, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27086

An 18.85 mW 20–29 GHz wideband CMOS low‐noise amplifier with 3.85 ± 0.25 dB noise figure and 18.1 ± 1.9 dB gain

AbstractA 20–29 GHz wideband CMOS low‐noise amplifier (LNA) with flat and low noise figure (NF), flat and high‐gain (S21), and excellent phase linearity property (group‐delay‐variation is only ±22.6 ps across the whole band) is demonstrated.To achieve flat and low NF, the size, layout, and bias of the input transistor were first optimized for minimum NF, and then the inductance of the input inductors was tuned to obtain a slightly under‐damped (flat) NF frequency response. In addition, to achieve flat and high S21 and small group‐delay‐variation, the inductive‐peaking technique was adopted in the current‐reused stage for bandwidth enhancement. The LNA consumed 18.85 mW power and achieved flat and low NF of 3.85 ± 0.25 dB, and flat and high S21 of 18.1 ± 1.9 dB over the 20–29 GHz band of interest. These are the best NF and S21 performances ever reported for a 21.65–26.65 GHz or a 22–29 GHz wideband CMOS LNA. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 2017–2020, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25380

A Transformer Noise-Canceling Ultra-Wideband CMOS Low-Noise Amplifier

Previously reported wideband CMOS low-noise amplifiers (LNAs) have difficulty in achieving both wideband input impedance matching and low noise performance at low power consumption and low supply voltage. We present a transformer noise-canceling wideband CMOS LNA based on a common-gate topology. The transformer, composed of the input and shunt-peaking inductors, partly cancels the noise originating from the common-gate transistor and load resistor. The combination of the transformer with an output series inductor provides wideband input impedance matching. The LNA designed for ultra-wideband (UWB) applications is implemented in a 90nm digital CMOS process. It occupies 0.12mm2 and achieves |S11| < -10dB, NF < 4.4dB, and |S21| > 9.3dB across 3.1-10.6GHz with a power consumption of 2.5mW from a 1.0V supply. These results show that the proposed topology is the most suitable for low-power and low-voltage UWB CMOS LNAs.

An inductorless wideband noise-cancelling CMOS low noise amplifier with variable-gain technique for DTV tuner application

In this paper, we propose an inductorless CMOS wideband low noise amplifier (LNA), operated in the range from 100 to 900 MHz, with current reuse, mirror bias, gain control and input matching device using noise-cancellation technologies. The traditional wideband LNAs have different input reflection coefficient parameters (S11) at different gain control modes, and they always implement with inductors for wideband matching. Therefore, the proposed LNA which can save power consumption at low gain mode, and implement without inductor on its design. Moreover, its S11 parameter has smaller variation at different gain control modes. The wideband CMOS LNA for digital video broadcasting-handheld (DVB-H), terrestrial-digital multimedia broadcasting (T-DMB), and digital video broadcasting-cable (DVB-C) tuner application is designed using TSMC 0.18 - μ m RF CMOS process. The post-simulation results at high gain mode show that the gain is 13 – 15.8 dB , the noise figure (NF) is less than 2.75 dB. The LNA consumes power between 7.25 mW (low gain mode) and 17.8 mW (high gain mode) at 1.8 V power supply. The core area is 0.435 × 0.67 mm 2 .

A 3–8 GHz Low-Noise CMOS Amplifier

A wideband CMOS low-noise amplifier (LNA) is proposed by using the concept of mutual coupling technique implemented through a symmetric center-tap inductor. A frequency widening network is designed with a center-tap inductor at the input and the output of an LNA to achieve bandwidth extension with a single stage amplifier. The proposed wideband low noise amplifier is implemented in the 0.18 mum CMOS technology. This design obtains a bandwidth of 3-8 GHz with a power consumption of 3.77 mW from a 1.8 V supply.

A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 mum CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under -9 dB in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 mm2.

0.5 V ultra-low power wideband LNA with forward body bias technique

An ultra-low power wideband CMOS low noise amplifier (LNA) fabricated in TSMC 0.18 µm RF CMOS process for sub 1 GHz applications is presented. The capacitive cross-coupled LNA with forward-body-bias (FBB) technique is adopted to achieve wideband input impedance matching and low power, low noise factor. The LNA is tested in the frequency range of 400–900 MHz, and exhibits a voltage gain of 18.5–20.7 dB, and a noise figure of 2.95 dB, drawing only 0.385 mW from 0.5 V power supply.

Design method for CMOS wide-band low noise amplifier for mobile TV application

A design method for wide-band CMOS low noise amplifier (LNA) is presented, which is suitable for mobile TV application. The proposed method integrates two kinds of wide-band LNA topologies by different switches, which can achieve better performance and avoid shortcomings when it operates at different modes. It can save the power consumption and improve the linearity at higher input signal power, and it also can reduce the noise at lower input signal power. The proposed wide-band LNA topology for mobile TV application is designed in TSMC 0.18-µm RF CMOS process.

Comparative analysis of wideband CMOS low-noise amplifiers for the RF range

A formalized method is presented for the circuit design of wideband low-noise amplifiers (LNAs) for RF applications. For a variety of LNAs thus obtained, a comparative performance analysis is performed by computer simulation in the frequency domain, involving optimization of small-signal LNA models. Optimal designs are thus identified showing a low reflection coefficient and a high gain over a wide frequency range extending to several gigahertz. Account is taken of limitations imposed by existing manufacturing technologies. For the sake of simplicity, the LNA configurations considered do not include frequency-selective networks.

A Highly Linear Wideband CMOS Low-Noise Amplifier Based on Current Amplification for Digital TV Tuner Applications

A differential wideband low-noise amplifier (LNA) based on the current amplification scheme is presented for digital TV tuners. In order to highly improve the linearity and exploit the noise cancellation, a common-gate stage with positive current feedback is integrated in parallel with a common-source stage using the current mirror amplifier. The proposed 0.18-mum CMOS LNA exhibits a power gain of 20.5 dB, an IIP3 of 2.7 dBm, an IIP2 of 43 dBm, and an average noise figure of 3.3 dB with 32.4 mW power consumption at a 1.8-V power supply and 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

Sub-0.2 dB Noise Figure Wideband Room-Temperature CMOS LNA With Non-50 $\Omega$ Signal-Source Impedance

This paper presents a wideband low-noise amplifier (LNA) designed to be used as the first stage of the receiver in the Square Kilometer Array radio telescope. The LNA design procedure and its layout features are discussed. The noise figure optimization procedure determines the signal-source resistance that results in reduced noise figure. When used in the radio telescope, the required signal-source resistance will be presented by the telescope custom-made antenna elements. The LNA, designed in 90 nm bulk CMOS, achieves sub-0.2 dB noise figure from 800 MHz to 1400 MHz, return loss of more than 11 dB, gain of more than 17 dB driven into a 50 load, output 1 dB compression point of 2 dBm, output IP3 of 12 dBm, and output IP2 of 22 dBm while consuming 43 mA from a 1 V supply. In the LNA implementation presented in this paper the load choke inductor and the source inductor are integrated whereas the gate-, bias-, and the choke-inductor between two transistors of the cascode are external. The noise figure of the presented LNA is to our knowledge the lowest noise figure achieved by a power matched wideband CMOS LNA at room temperature.

High-Gain Wideband CMOS Low Noise Amplifier with Two-Stage Cascode and Simplified Chebyshev Filter

An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-μm CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.

A Low-Power Wideband CMOS LNA for WiMAX

In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply. The chip performance achieves S11 below -10 dB across the entire band and a minimum noise figure of 2.55 dB. The simulated third-order input intercept point is -2.7 dBm. The voltage gain reaches a peak of 11.2 dB in-band with an upper 3-dB frequency of 3.8 GHz, which can be extended to reach 6.2 GHz using shunt inductive peaking. A figure of merit is devised to compare the proposed designs to recently published wideband CMOS LNAs

Wide-band CMOS cascode low-noise amplifier design based on source degeneration topology

A design methodology for a wide-band CMOS low noise amplifier (LNA) with source degeneration is presented. By allowing an arbitrary source degeneration and employing a general input matching network, the proposed wide-band CMOS LNA can be shown for any choice of transistor width to achieve the minimum noise figure at all frequencies of interest. The transistor width simply affects the gain of the LNA at the cost of power dissipation. These results apply uniquely to CMOS LNAs, as they are derived from a quasi-static MOSFET model. To validate these design concepts, a wide-band LNA was realized in 0.25-/spl mu/m CMOS technology. The measured noise figure ranges from 2.7 to 3.7 dB over 3.2-4.8 GHz with power consumption of 20 mW. A close agreement with the theoretical results is observed.