Wallace Tree Research Articles

High Speed and Efficient Wallace Tree Multiplier for Dsp Applications

Multiplier is one of the key and fundamental block in the many applications such as DSP, signal processing etc. In numerous occasions multipliers plays a prominent role to decide the system performance. Out of the several multipliers wallace tree multiplier is one of reliable and occupies the minimal space in digital applications. This work describes the designing of the high performance 8 bit wallace tree multiplier using compressor technique. The multiplier were simulated and estimated its performance using the Vivado.

Implementation of High Speed Modulo (2 +1) Multiplier for IDEA Cipher

Abstract In this brief a new modulo 2n+1 multiplier is proposed for IDEA block cipher. A total of (n+1) partial products including a constant correction term are added using tree of Carry save adder with end around complemented carry followed by modulo adder. Wallace tree multiplier is adopted in order to improve the accumulation of partial products. Proposed modulo multiplier is compared with the other modulo multipliers available in the literature for IDEA block cipher. The VLSI implementation of proposed multiplier utilizing carry save tree architecture achieves (30 to 35%) improvement in the delay whereas Wallace tree architecture achieves (32 to 41.5%).

Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

Convolutional Neural Network (CNN) has attained high accuracy and it has been widely employed in image recognition tasks. In recent times, deep learning-based modern applications are evolving and it poses a challenge in research and development of hardware implementation. Therefore, hardware optimization for efficient accelerator design of CNN remains a challenging task. A key component of the accelerator design is a processing element (PE) that implements the convolution operation. To reduce the amount of hardware resources and power consumption, this article provides a new processing element design as an alternate solution for hardware implementation. Modified BOOTH encoding (MBE) multiplier and WALLACE tree-based adders are proposed to replace bulky MAC units and typical adder tree respectively. The proposed CNN accelerator design is tested on Zynq-706 FPGA board which achieves a throughput of 87.03 GOP/s for Tiny-YOLO-v2 architecture. The proposed design allows to reduce hardware costs by 24.5% achieving a power efficiency of 61.64 GOP/s/W that outperforms the previous designs.

Vedic Multiplier Implementation in VLSI

In processors the complex and challenging operations are needed to be handled to overcome the demands, which leads to an increase in processor cores. This leads to an increase in the load of the processor and can be limited by placing a co-processors under specific type of functions like signal processing. But anyhow the speed of the ALU replies on the multiplier. Since multipliers are the major components to perform operations in the CPU. To implement fast multiplication operations, Vedic mathematics are involved based on 16 sutras, each with its special characteristics. This technique usually reduces the area, power and delay of the processors. So the existing Wallace tree multiplier technique has been replaced by the Vedic multiplier algorithms based on two different sutras as Urdhva Tiriyagbhyam and Nikhilam algorithms. These types of multipliers were designed and specified using Verilog HDL and have been synthesized and simulated using Xilinx ISE project Navigator v. 14. 7 platform and then compared with the parameters like delay time, area (Number of sliced LUT's and Number of bonded IOB's) and power in 32, 64 and 128 binary bit multiplication

Design of Parity Preserving Reversible DIF-FFT using 90nm Technology

Reduction of power consumption is the major goal in modern circuit design. Reversible logic gate do not lose any information & thus have zero power dissipation. In all signal processing applications, the most important computation involved is Fast Fourier Transform (FFT). For the fault tolerance computation parity preserving logic can be used .The authors present an efficient parity preserving reversible DIF-FFT using 90nm technology. The implementation involves the design of DIF-FFT with reversible P2RG along with Fredkin gate over different combinations of adders (Carry look ahead adder (CLA), Carry save adders (CSA), Carry skip adder (CSK) & Ripple carry adder (RCA)) & multipliers (Array Multiplier (AM), Carry Save Multiplier (CM), Parallel Multiplier (PM), Wallace Tree Multiplier (WM)). DIF-FFT Architectures of different combinations were coded using Verilog & the same was simulated by Modelsim 6.3f. Parameters such as Hardware Device utilization & Power analysis were done using Quartus II 9.0 with respect to Stratix II device which works on 90nm technology. It was found that DIF-FFT Architecture designed using CSA & CM uses lesser resource utilization whereas architecture designed using CSA & AM has lesser Power dissipation by 72% & 81% respectively.

Design of low power multi-ternary digit multiplier in CNTFET technology

This work introduces the method to implement energy efficient designs of arithmetic units such as a ternary full adder, ripple carry adder, single-trit multiplier and multi-trit multiplier using carbon nanotube field effect transistors (CNTFETs). A CNTFET unique feature of the threshold voltage variation by changing the CNT diameter, make it a suitable alternative for being employed in ternary logic designs. In designing the proposed circuits, decoder circuit functionality is realized by various threshold detector circuits tuned to a specific logical threshold voltage value. The multiplier circuit is designed by combing the capacitive logic and the minority function. In order to test the practicability of proposed circuits in cascaded circuits, multi-digit adder and multiplier circuits are constructed. The proposed multi-digit multiplier structure is based on classical Wallace multiplier and includes various optimized versions of adder and multiplier circuits. Extensive simulation has been done to examine the competency of proposed designs under different test conditions. The design of 3-trit multiplier formed by combing the proposed adder and multiplier circuits shows 16 times reduction in power consumption as well as energy consumption in comparison to previous multiplier design.

Efficient design of QCA based hybrid multiplier using clock zone based crossover

Quantum-dot cellular automata (QCA) is an emerging trend in nanotechnology and appropriate for the development of high performance and low power integrated circuit design. Dadda and Wallace tree multipliers are designed by employing CZBCO technique to overcome the crossover issues of geometric design complexity and alignment accuracy and also to achieve high device density. The proposed design of QCA-based Hybrid parallel multiplier consists of decomposing structure that adopts Dadda and Wallace algorithms to optimize the design. In this proposal, N-bit multiplier array is decomposed into four N/2-bit multiplier arrays that are easily constructed by employing both Wallace and Dadda multipliers. The Hybrid multiplier comprising dadda and Wallace tree multiplier uses less number of majority gates and inverters and hence minimizes area, cell count and delay. It has been observed that the QCA cost function of the proposed multiplier better than existing multiplier referred in the literature in terms of energy and speed. Furthermore, the proposed multiplier significantly achieves high device density, lessened clock delay, area and cell count and also to eliminate fabrication difficulty of crossover.

Design Of Dadda And Wallace Tree Multiplier Using Compressor Technique

The work portrays about the design of the Dadda multiplier using 4:2 compressor techniques. The three design techniques, namely conventional design, optimized design using exclusive OR with multiplexer and a further optimized design with less number of critical paths with gates are implemented. All the three designs are implemented in Dadda multiplier and wallace tree multiplier and their performances are compared. The performance metrics measured are area, power consumption, delay and transistor count and these parameters are efficient in dadda multiplier compared to wallace tree multiplier with the above three design techniques. The designs are using behavioral modeling and the results are taken in the 180nm Cadence tool. The result shows that the Dadda multiplier performs better in terms of delay, area and transistor count for all three designs than the Wallace tree multiplier.

High Performance of Wallace Tree Multiplier Stacking Circuit

In this paper one novel double counter proposed which is quick when contrasted with another normal's parallel counters. First, we are designing binary counter using solely full adders, and after with new symmetric stacking method. We are evaluating these two techniques and displaying how the symmetric stacking method is decreasing the x-or gate delays in the essential route of the binary counter. This kind of our proposed counter is very useful in the existing counter based totally Wallace tree multiplier design. With this new symmetry stacking counter we are lowering delay and increasing the performance of multipliers in VLSI circuits. We are designing and simulating our proposed quick binary counter using Xilinx ISE layout suite14.7.

Systematic synthesis of approximate adders and multipliers with accurate error calculations

In this study, we perform logic synthesis and area optimization of approximate ripple-carry adders and Wallace-tree multipliers with a given error constraint. We first implement approximate 1-bit adders having different error rates as building blocks of the proposed multi-bit adders and multipliers. In implementations, we exploit offsetting errors in carry and sum outputs of the adders. Also we take into account the probability of occurrence of input assignments. Using the implemented 1-bit adders, we systematically synthesize multi-bit adders and multipliers proceeding from the least to the most significant bits. We design the ripple-carry adders such that their successive 1-bit approximate adders cannot produce build-up errors. We design the Wallace-tree multipliers by considering the fact that their building blocks of 1-bit adders might have different probabilities of occurrence for different input assignments. As a result, the proposed adders and multipliers, implemented using the Cadence Genus tool with TSMC 0.18μ m CMOS technology, offer in average a 25% smaller circuit area, and correspondingly power consumption, compared to the circuits proposed in the literature by satisfying the same error constraint. We also evaluate the adders and multipliers in image processing applications as well as within artificial neural networks.

Symmetric Stacking Based Fast Binary Counter Using Modified Gate Diffusion Input (M-GDI) Technique

In this paper, modified-Gate Diffusion Input (M-GDI) based binary counter is designed using symmetric stacking method. The binary counter is designed using 3-bit stacker circuit that groups the one bit together and symmetric method is used to form 6-bit stack. The 6-bit stack is converted to binary count to produce required counters. The M-GDI is used to further reduce the transistor count than the CMOS logic transistor count. Mainly the basic gates are developed using the M-GDI technique and the basic gates are replaced in the 6:3 counters to further improve counter-performance. The proposed 6:3 binary counter has no Exclusive or gate (XOR) gates on the critical path, which leads to faster performance of the circuit. The proposed counter is faster, also consumes less power than the traditional. By using this proposed counter in Wallace multiplier, the delay and power for higher-order multipliers is reduced. This paper proposes a novel symmetric stacking based fast binary counters using the modified gate diffusion input (M-GDI) technique. This paper proposes a novel binary counter.

Design of Advanced Multiplier using 15-4 Compressor

The major role of electronics device is to provide low power dissipation and compact area with high speed performance. Among the major modules in digital building blocks system, multiplier is the most complex one and main source of power dissipation. Approximate Computing to multiplier design plays major role in electronic applications, like multimedia by providing fastest result even though it possesses low reliability. In this paper, a design approach of 16 bit Wallace Tree approximate multiplier with 15-4 compressor is considered to provide more reliability. The 16×16 Wallace tree multiplier is synthesized and simulated using Xilinx ISE14.5 software. The multiplier occupies about 15% of total coverage area. The dissipated power and delay of the multiplier are 0.042μw, 3.125ns respectively.

Novel Architecture for Binary Multiplication

Multipliers is the basic unit for all signal processing applications and other applications. In all technology advancement it plays a vital role, the targets are low power consumption, increase in speed, reduction in area etc. The computations that are done by a modern computers that includes microcomputers and microprocessor is astronomical. Even with the high speed computer chips the process of the data coming from the devices all over the world requires efficient algorithms and to achieve the compatibility we need to use the chip area effectively. The most often encountered computation in data processing or signal processing is the operation of multiplication. This architecture is to present a novice solution to reduce the total area of the multiplier by modifying the partial products addition multiplier. Generally, to compute the data with high speeds modern hardware uses the Wallace tree or dadda multiplication techniques. By reducing the number of partial products addition the number of gates can be reduced used to obtain the final result. In this proposed method we reduced the real-estate of the chip by using more number of full adder in the earlier stages of the partial products addition which is not present in the conventional multipliers.

An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform

<span lang="EN-US">In digital image processing, the compression mechanism is utilized to enhance the visual perception and storage cost. By using hardware architectures, reconstruction of medical images especially Region of interest (ROI) part using Lossy image compression is a challenging task. In this paper, the ROI Based Discrete wavelet transformation (DWT) using separate Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM) methods are designed. The Lifting based DWT method is used for the ROI compression and reconstruction. The 9/7 filter coefficients are multiplied in DWT using Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM). The designed Wallace tree multiplier works with the parallel mechanism using pipeline architecture results with optimized hardware resources, and 8x8 Vedic multiplier designs improves the ROI reconstruction image quality and fast computation. To evaluate the performance metrics between ROI Based DWT-WM and DWT-VM on FPGA platform, The PSNR and MSE are calculated for different Brain MRI images, and also hardware constraints include Area, Delay, maximum operating frequency and power results are tabulated. The proposed model is designed using Xilinx platform using Verilog-HDL and simulated using ModelSim and Implemented on Artix-7 FPGA device.</span>

변형 4-3 압축기와 소거법을 이용한 10-Bit Wallace Tree 곱셈의 설계 및 구현

대부분의 고성능 디지털 시스템에서 곱셈기는 매우 중요한 블록이다. 전통적으로 Wallace Tree 곱셈기는 CSA(Carry Save Adder)를 기반으로 구현한다. 본 논문에서는 FPGA를 이용하여 작은 인공지능망(small AI networks)을 구현할 때, 기존의 CSA와 변형 4-3 압축기를 이용하여 고속 곱셈기를 구현하는 새로운 방법을 제안한다. 특히, 변형 4-3 압축기와 소거법을 이용한 10 비트 Wallace Tree 곱셈기를 제안하였다. 그리고 이를 검증하기 위하여 Verilog-HDL를 이용하여 구현하고 이를 Xilinx ISE 14.7을 이용하여 검증을 수행하였다. 제안된 설계 방법은 전통적인 Wallace Tree 곱셈에 비하여 19.1%, 소거법에 비하여 6.2%의 지연시간을 감소시켰다.

Implementation of multi-precision floating point divider for high speed signal processing applications

The introduction of fused multiplier and add technique enhances design metrics of floating point (FP) arithmetic operations. Particularly Newton–Raphson (NR) based division algorithm is popular choice to SRT division algorithms. This paper proposes 32-bit FP division using NR computational division technique with pipelining method capable of doing high speed signal processing operations. The proposed divider used as IP core and make it as optimal choice to speed up FP operations. It improves rounding accuracy in addition with reduction in area overhead. The NR computational calculations are implemented by iteratively using 32-bit FP multiplier and adder. The key module used for calculating significand (mantissa) part is 24-bit Wallace tree multiplier using carry save adders. The Wallace multiplier provides higher computational speed, hence, is effectively utilized as a part of FP divider. The proposed pipelined FP divider is fully combinational circuit with clock and data gating applied to reduce the dynamic power consumption, delay and area overhead designed for signal processing applications. It also improves the accuracy of the result. The operands are represented and operated using IEEE 754 standard. The operation and results are validated through simulation using VIVADO software and implemented on Xilinx-7 series, ARTIX field programmable gate array.

Toward Verifying Nonlinear Integer Arithmetic

We eliminate a key roadblock to efficient verification of nonlinear integer arithmetic using CDCL SAT solvers, by showing how to construct short resolution proofs for many properties of the most widely used multiplier circuits. Such short proofs were conjectured not to exist. More precisely, we give n O (1) size regular resolution proofs for arbitrary degree 2 identities on array, diagonal, and Booth multipliers and n O (log n ) size proofs for these identities on Wallace tree multipliers.

Design and Simulation of a Nanoscale Threshold-Logic Multiplier

Multiplication is one of the most important operations in microprocessors and digital signal processing systems. Different multiplier architectures have been proposed in the literature. One of the most widely used architecture is the Wallace tree multiplier. This multiplier is known for its high speed. However, it occupies a large area. In this paper, we used Threshold Logic Gates instead of conventional logic gates to reduce the area. The multiplier was designed in 65nm CMOS technology, and achieved 28% reduction in the number of transistors compared to the one with conventional logic gates. It also achieved a lower power-delay-product.

Performance Evaluation of Wordlength Reduction Based Area and Power Efficient Approximate Multiplier for Mobile Multimedia Applications

Hardware multiplier circuits decide the speed and power consumption in the execution of digital signal processing algorithms. The desirable feature of reduced area and power consumption for battery-driven multimedia gadgets can be realized by replacing the power hungry multiplier circuits with approximate multiplier circuits. The approximation techniques reduce the complexity of the design and improve the energy efficiency of the circuit. This paper proposes an area and power efficient approximate unsigned integer multiplier architecture based on wordlength reduction. It is designed to meet a pre-specified error performance with improved area and power reduction compared with similar designs. It is extended further for the signed multiplier architecture. The circuit characteristics are analyzed to establish the suitability of the proposed design for low-power applications. Synthesis results show that the proposed unsigned multiplier consumes 65% less power than the exact Wallace multiplier. The area requirement of the proposed multiplier reduces by 50% compared to an exact multiplier. The multiplier is tested for image filtering to establish the efficacy of the design in multimedia applications.

Design of a low power, double throughput cyclic combinational gate diffusion input based radix-4 MBW multiplier and accumulator unit for on-chip RISC processors of MEMS sensor

Modern microsystems based on sensor specific structures have robust on-chip digital signal processors to process the input signals. In order to improve the robustness of the system, on-chip processor circuitry has to be fabricated in limited areas with low latency and low power consumption. In this paper, a new technique for implementing low-power, high performance multiplier and accumulator (MAC) unit has been introduced for on-chip microelectromechanical systems applications. Based on cyclic combinational gate diffusion input technique, the proposed MAC unit is designed using Radix-4 modified Booth Wallace multiplier architecture and can operate up to 100 MBps of input data acquisition rate. Our proposed design is made of single threshold voltage transistors which employ low latency and reduced power consumption and less complexity in physical design. CAD tool based simulation at Generic 250 nm technology and comparison between proposed design with other available designs shows that the proposed design is better than many other designs for similar range of operation. The proposed design has an average power consumption of 98.8 mw and propagation delay of 6.8 ns at input bit rate 100 MBps for 16 bit operands.