Vedic Multiplier Implementation in VLSI

Abstract

In processors the complex and challenging operations are needed to be handled to overcome the demands, which leads to an increase in processor cores. This leads to an increase in the load of the processor and can be limited by placing a co-processors under specific type of functions like signal processing. But anyhow the speed of the ALU replies on the multiplier. Since multipliers are the major components to perform operations in the CPU. To implement fast multiplication operations, Vedic mathematics are involved based on 16 sutras, each with its special characteristics. This technique usually reduces the area, power and delay of the processors. So the existing Wallace tree multiplier technique has been replaced by the Vedic multiplier algorithms based on two different sutras as Urdhva Tiriyagbhyam and Nikhilam algorithms. These types of multipliers were designed and specified using Verilog HDL and have been synthesized and simulated using Xilinx ISE project Navigator v. 14. 7 platform and then compared with the parameters like delay time, area (Number of sliced LUT's and Number of bonded IOB's) and power in 32, 64 and 128 binary bit multiplication