Wallace Tree Research Articles

Design and Implementation of RISC-V Based Pipelined Multiplier

Among the many microprocessors, RISC-V as an open-source instruction set is gradually gaining popularity among academia and industry. The performance of the multiplier in the microprocessor imposes constraints on the computational power of the processor. In order to improve the efficiency of multiplication instructions, a pipeline multiplier is implemented in this paper. Firstly, the partial product is generated using the Radix-4 booth. Secondly, the Wallace tree structure is used to accelerate the compression of the partial product. Then, a parallel prefix adder is used to calculate the resulting partial product to improve the timing. Finally, registers are added as a pipeline to achieve a high-efficiency multiplication calculation. With the operating voltage and temperature set to typical conditions, the integrated multiplier area is 50260.6 μm2, and the power consumption is 20.41 mW. The final frequency of the multiplier is 1 GHz in gate-level simulation.

A novel sign detection method in residue number system based on Chinese remainder theorem with fractional values

Sign detection is a non-modular operation in the residue number system (RNS). It requires the calculation of the number positional characteristic represented in the RNS. This work proposes a new sign detection method based on the Chinese Remainder Theorem (CRT) with fractional values implemented using the Wallace tree and the modified Kogge-Stone adder. Hardware modelling on FPGA for the proposed method shows that it provides 1.3 – 36.3 times less hardware costs than the other state-of-the-art (SOTA) methods, and for ASIC modelling the proposed method provides 1.14 – 35.74 times less hardware costs than the other SOTA methods. The presented sign detection method can be helpful in RNS-based devices in implementing comparison and division operations, providing an extension of the RNS application in areas such as cryptography, machine learning, and digital signal processing.

Enhanced Quasi-Static Energy Recovery and Modified Clock Gating for the Wallace Tree Multiplier with Reversible Adders

High-speed, low-power digital circuits are essential in many digital applications. The objective of the paper is to design high-speed low-power multipliers with reversible gates. The realization of a multiplier with an efficient clocking system is also presented to reduce leakage power consumption. The existing reversible configurations do not possess an effective clocking system for reducing power in an idle state. In this work, a modified clock gating (MCG) and Enhanced Quasi-Static Energy Recovery Logic (EQSERL) are designed to generate a clock pulse. The EQSERL reduces the dynamic state in the circuit and it is designed with reduced complexity. This process effectively reduces leakage power consumption in the circuit. The conventional clock gating circuit is modified for connecting it with the EQSERL. This MCG circuit reduces unwanted power consumption. The conventional Wallace tree multiplier (WTM) involves full adder and half adder circuits. In this proposed work, a square root carry select adder (SQRT CSLA) with a reversible binary to excess-1 converter (BEC) and a ripple carry adder is presented. The reversible gates such as the Feynman gate, the Toffoli gate, and the dual key gate are employed. Finally, the proposed architecture is tested with different clocking circuits using Synopsys tools and the performance metrics like delay and power are observed.

FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder

ABSTRACT Nowadays, the application of computations and communications is needed for high performance, reduced size and lower power utilisation. The multiply and add functions are one of the frequently used operations in digital signal processing. Various types of multipliers are available in digital Various types of multipliers are available for various Signal processing applications.. Among these multipliers, Vedic multiplier is one of the most optimised multipliers used in a signal processing module. In the existing method, the Vedic multiplier is designed with conventional adders, which is having higher area utilisation, lower speed and higher power consumption. Hence, the modified Vedic multiplier is proposed to improve the speed of multiplication using hybrid technology. The partial products of the proposed multiplication are added using 2 × 2 Vedic multiplier and hybrid carry select adder (binary to excess one converter (BEC), Han-Carlson adder and Multiplexer). The critical path delays of hybrid 4 × 4 Vedic multiplier are the summation of 2 × 2 Vedic multiplier, two full adders, two multiplexers and two BECs for producing the final product. The proposed hybrid Vedic multiplier is operated at high speed with reduced size as compared to the existing multiplier techniques. The proposed hybrid Vedic multiplier is designed and simulated using Verilog HDL and implemented in Spartan 6 field-programmable gate array device. The implementation results showed that the delay of the proposed multiplier gets ameliorated as compared to array multiplication (30.84%), Wallace tree multiplication (29.52%), multiplication based on compressor (23.71%), Vedic multiplication by carry look-ahead adder (22.91%), Vedic multiplication by ripple carry adder (14.45%), revised booth multiplication (15.42%) and Vedic multiplication by Han-Carlson adder with BEC (13.95%) and hybrid multiplier (11.37%).

Design of Complex Multiplier Using Vedic Mathematics

In this project, a 4x4 multiplier is implemented that utilizes the Urdhava Tiryakbhyam sutra method in Vedic mathematics. This method is applicable in all two decimal number multiplications which offers high speed calculation and improved efficiency. Thus, the design of a 4x4 Vedic-based multiplier is solely aimed at performing faster multiplications and achieving quicker processing speeds than the traditional multipliers. The architecture of the Vedic multiplier consists of four 2x2 multipliers and three adders of different bit sizes that are assembled using the Wallace tree implementation. The coding for the multipliers and adders is written in Verilog Hardware Description Language (HDL) in the Quartus Prime 17 Software. Functional simulation is then carried out to ensure that the Vedic multiplier performs the accurate multiplication operations, while the Verilog Compiled Simulator is employed to compile and simulate the multiplier design. Following this, the Design Compiler (DC) and Integrated Circuit Compiler (ICC) command scripts are then composed to allow the logic and physical synthesis to be performed on the Vedic and traditional multipliers. From there, the performance level of both these multipliers are assessed through reference to several key parameters such as timing, area, power consumption, overflow percentage and congestion statistics. Based on the results obtained in the synthesis process, the Vedic multiplier possesses faster operational speed than the traditional multiplier (due to a shorter processing time), butultimately exhibits a greater power consumption and wider area coverage.

High Performance, Low Power Wallace Tree Multiplier

An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI applications is multipliers. To enhance the performance of circuits and systems, the design of multipliers is very important. The key feature of a high-performance Wallace tree multiplier lies in its efficient reduction of partial product additions. By utilising a combination of carry-save and carry-propagate adders, it minimises the critical path delay and maximises the speed of multiplication. Additionally, advanced optimisation techniques such as parallel prefix adders and parallel carry-save adders can be employed to further improve performance.

Design of (3,2) and (4,2) CNTFET Ternary Counters for Multipliers

The reduction trees of combinational multipliers are widely applying counters. To be able to compare the ternary and the binary approaches, Nanotube Field-Effect Transistor (CNTFET) ternary (3,2) and ternary (4,2) counters have been designed. The ternary (4,2) counter is compared with the binary (7,3) counter as both compute approximately the same amount of information. The binary counter is more efficient. However, comparing counters is not enough: in the Wallace reduction tree of the ternary multiplier, there are two times more lines to reduce compared to the binary one, as a 1-trit multiplier generates both product and carry terms. Comparing the Wallace tree of an 8*8-trit multiplier and a 12*12-bit binary one also shows that the binary implementation is the most efficient.

Design and implementation of an 8-bit approximate Wallace Tree Multiplier for energy efficient deep neural networks

Design and implementation of an 8-bit approximate Wallace Tree Multiplier for energy efficient deep neural networks

High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system

Multiply-Accumulate (MAC) units have been developed recently for various high-performance applications. A crucial component of computing devices, particularly embedded systems, is the MAC unit. The fundamental MAC unit is composed of Multiplier, Adder, and Accumulator. The input for the MAC unit is read from memory cells and given to the MAC multiplier block that multiplies the inputs and passes the result to an adder, which stores the result in memory. One clock cycle is required to complete the full operation. In this manuscript, a lesser power higher speed MAC unit is proposed for Embedding system. High speed binary carry select adders are utilized in MAC units for their speed and integration with three different blocks includes half sum with carry generators (HSCG), final carry generators (FCG), and final sum generators (FSG). For Multiplier design in MAC unit, the counter-based modular Wallace tree multiplier (CMWTM) is utilized, which has power-saving techniques. The proposed CMWTM-HSBCSA-ES MAC unit is implemented in Virtex FPGA development board utilizing Verilog programming language in Xilinx ISE 14.5 design tools. The efficacy of proposed design can be assessed with the metrics such as area, delay, dynamic power consumption, energy, normalized energy and speed. Then the performance of the proposed design provides 16.58%, 41.57% and 25.44% higher speed, 50%, 3.08% and 36% lower delay and 28.03%, 24.50% and 50.32% lower energy compared with the existing MAC unit designs, such as AxMAC-ES, a higher performance MAC unit through incorporating additions with accumulations into partial product reduction procedure (PPR-BA-ES) and high-accuracy MAC technique for unary stochastic computing (TE–SC–ES) respectively.

Design and Evaluation of Multipliers Using Simulated Annealing and Partitioning Approach

Multipliers are widely used in various fields of engineering, and they are considered to have complex designs. The efficient design of multipliers to meet various design requirements is still an active area of research. In this paper, a thermo-inspired metaheuristic called population-based simulated annealing algorithm, for the design of multipliers using four different resource types, is proposed. Metaheuristics suffers from the problem of scalability and non-convergence as the size and complexity of the circuit increase. Four types of partitioning approaches- output, input, input-output and hybrid-output partitioning are proposed to overcome the same. Proposed partitioning approaches have increased the success rate and reduced the time to realize the circuit. The multipliers designed are synthesized on Cadence Genus with 90 nm technology and compared with traditional designs such as Array, Wallace tree, Dadda and Booth multipliers to conclude that metaheuristics are capable of generating near-optimal solutions in terms of power, area and delay.

Design of Wallace Tree Encoder for Flash ADC

Analog to digital converter plays a very important role in today’s digitized world as they have wide range of applications. Wallace tree encoder is an effective hardware implementation in VLSI circuits that is utilized for the analogue to digital conversion process. The Wallace tree encoder transforms thermometer code into binary code in an ADC. The suggested flash digital to analogue converter confirmed the energy, and speed. The proposed technique provides Less Delay, Less Power Consumption, and a lesser number of transistors compared to existing techniques. In this project, the proposed transmission gate full adder technique provide Less Delay, Less Power Consumption, Better Power Delay Product and a lesser number of transistors. The proposed encoder is made to count the 1s available to the logic gates for designing ROM encoders and fat tree conversion. The power may be conserved by building a low power, high performance Wallace tree encoder implementing transmission gate logic and modified full adders since Wallace tree encoder uses more power. The proposed system focuses at lowering the transistor count to improve power efficiency and delay comparator, and it is effective in minimizing the bubble errors. The Wallace tree encoder is designed by using transmission gate based full adder circuits. The proposed designs are designed and simulated using LTspice Tool with 45nm CMOS technology. The power consumption of the encoder circuit must be decreased in order to create a low power Flash ADC. The power consumption of this encoder changes noticeably when the internal full adder circuit is modified

Approximative Signed Wallace Tree Multiplier Using Reversible Logic

Abstract: The bulk of high-performance and information systems, including microcomputers and digital signal processors, have multipliers as an essential piece of hardware. Convolutional unit are the computationally demanding and performancedetermining operating units in the vast majority of signal conditioning applications. Its length, latency, and power for convolution units, which largely employ adders and multiplyers, are strongly influenced by multipliers. Multimedia and convolution neural networks, which employ processing units, are two examples of real-world applications that place a high demand on high speed multipliers which are optimised both size and power. This project presents an innovative approximation sign Wallace tree multiplication with a approximative 4:2 compressor. Reversible circuitry improves the design for implementation.

Methods and hardware to accelerate the work of a convolutional neural network

Three main approaches to building computer systems are analyzed and allocated: software, hardware, and problem-oriented. A problem-oriented approach was chosen for the implementation of CNN. This approach uses a processor core with hardware accelerators that implement basic CNN operations. The development of computer systems for the implementation of CNN should be carried out based on an integrated approach. This approach includes a modern element base, existing hardware, and software for the implementation of the CNN; methods and algorithms for the implementation of CNN; methods, algorithms, and VLSI structure for the implementation of basic operations of the CNN; methods and means of computer-aided design of hardware and software focused on the implementation of CNN computer systems. For the development of computer systems for the implementation of CNN chosen approach, which includes: variable composition of equipment; use of the basis of elementary arithmetic operations; organization of the process of calculating the scalar product as execution single operation; pipeline and spatial parallelism; localization and simplification of links between the steps of the conveyor; coordination of the time of formation of input data and weighting coefficients with the duration of the conveyor cycle. It is shown that in order to reduce the processing time of large images, it is most expedient to use parallel-stream VLSI -implementation of basic operations. The modified Booth algorithm for forming partial products in a parallel-threaded computing device is selected, which decreased the number of steps in the pipeline. The method of group summation has been improved, which, with multi-input single-digit adders, combined according to the principle of the Wallace tree, provides a reduction in summation time. The method of parallel-flow calculation of scalar product in a sliding window is developed, which, by coordinating the time of receipt of columns of input data and weighting coefficients with the duration of the conveyor cycle, provides high efficiency of equipment use and calculations in real-time. The main ways regarding coordination of the time of receipt of input data columns and weighting coefficients with the duration of the conveyor stroke of hardware that implement two-dimensional convolution are determined. The hardware structure for the realization of two-dimensional convolution in a sliding window, which is focused on VLSI- implementation with high efficiency of equipment use, has been developed. Programmable logic integrated circuits selected for the implementation of hardware accelerators. Single-bit 7, 15, and 31 input adders were developed and modeled on the basis of FPGA EP3C16F484 of the Cyclone III family of Altera company, and an 8-input 7-bit adder was synthesized on their basis.

Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier

<span lang="EN-US">In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.</span>

Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder

Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder

Comparison and design of energy-efficient approximate multiplier schemes for image processing by CNTFET

ABSTRACT Approximate computing is an emerging paradigm that can tolerate some loss of accuracy to improve the energy consumption and design complexity. Multiplication is one of the important computational components in various digital signal processing (DSP) applications. Improvement of multipliers, as the building blocks of an approximate computing systems, has received significant attention. Compressors are key elements in an approximate multiplier to have an optimal design with high performance. This paper proposes an approximate/exact 4–2 compressor and an exact 5–2 compressor in carbon nanotube field-effect transistors (CNTFET) technology for utilisation in an approximate multiplier. Four efficient designs for utilising the proposed compressors are introduced and analysed for a Wallace multiplier. All of the proposed circuits are analysed in 32 nm CNTFET Stanford technology and are simulated by HSPICE. In addition, as an image processing application of approximate multipliers, this paper compares the quality metrics of the image multiplication for the proposed designs and previously presented approximated multipliers. For example, the proposed schemes provide excellent results in structural similarity index up to 99%, and peak signal-to-noise ratio more than 45 dB. Also, it uses figure of metric (FOM) that includes the accuracy and quality metrics of the approximate multipliers. The simulation results demonstrate the efficiency of proposed designs.

Design of approximate Booth multipliers based on error compensation

With the rapid development of the Internet of Things, terminal equipment is greatly restricted in hardware resources and power supply. Therefore, there is an urgent need for new low-power computing units. Aiming at the problem of high power consumption of the arithmetic unit, a low-power approximate Booth multiplier based on complementary error is proposed. Among them, the new Booth encoder will produce positive errors and the approximate Wallace tree structure will produce negative errors. The mutual compensation of the two errors can improve the accuracy of the approximate Booth multiplier to a certain extent. The experimental results show that, compared with the existing multipliers, the proposed approximate Booth multiplier reduces the power consumption by 20.62% and the delay by 14.45%, saving 19.68% of the area. At the same time, its normalized average error distance is better than the existing approximate multiplier. Finally, the results of image filtering verify the practicality of the proposed approximate Booth multiplier.

Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis

<p><span>The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with high-performance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson’s method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements.</span></p>

Fault simulation for design for testability inserted designs

<p>Systematic design for testability (DFT) is a technique to enhance the testability of design so that it is further organized and self-regulating. The objective of systematic DFT is to enhance a circuit's operability and evidence. This can be performed in a variety of ways. The scan pattern method is the extremely predominant, and it modifies the design's internal sequential circuitry. In this manuscript, frequently used industry standard functional register-transfer level (RTL) designs are chosen. Structured DFT approach is adopted to do scan insertion and automatic test pattern generation (ATPG) to enhance the testability. Proposed methodology provides the controllability and observability for the clocks and reset used in chosen RTL designs by eliminating S rule and D rule violations by adding test logic. Also able to insert stuck at faults and achieve fault coverage of 97.78% and test coverage of 99.26% for DFT architecture for Wallace tree multiplier design, and found different classes of faults as testable and untestable faults and also performed fault simulation for the intended designs to detect fault from the created deterministic patterns.</p>

A high‐efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression

SummarySophisticated systems take advantage of approximate circuits for energy management. A gate‐level structure is introduced to make a novel imprecise full adder (FA) cell by the gate diffusion input (GDI) strategy. The carbon nanotube field‐effect transistor (CNTFET) technology lowers the FA power, and the swing issue is resolved by the dynamic threshold (DT) technique. The FA specifications are 10 transistors, two internal nodes, 0.191‐μm2 area, three errors, and an error rate (ER) of 37.5%. Some inputs are directly passed to the final stage of the FA to reduce the delay and dynamic power. The FA is used in three 4:2 compressors with 12, 16, and 20 transistors, respectively. The compressors are based on the modified stacking concept to attain low power, small area, and high speed. The compressors are used up in the partial product reduction tree (PPRT) of a new 8‐bit inexact multiplier. Regarding the multiplier, the power–delay product (PDP) is decreased by 25.21%, and the normalized mean error distance (NMED) shows high accuracy. An imprecise discrete cosine transform (DCT) is implemented by the multiplier for image compression, and compared with the literature, the peak signal‐to‐noise ratio (PSNR) and structural similarity index metric (SSIM) are amended by 8.26% and 7.29%, respectively.