Enhanced Quasi-Static Energy Recovery and Modified Clock Gating for the Wallace Tree Multiplier with Reversible Adders

Abstract

High-speed, low-power digital circuits are essential in many digital applications. The objective of the paper is to design high-speed low-power multipliers with reversible gates. The realization of a multiplier with an efficient clocking system is also presented to reduce leakage power consumption. The existing reversible configurations do not possess an effective clocking system for reducing power in an idle state. In this work, a modified clock gating (MCG) and Enhanced Quasi-Static Energy Recovery Logic (EQSERL) are designed to generate a clock pulse. The EQSERL reduces the dynamic state in the circuit and it is designed with reduced complexity. This process effectively reduces leakage power consumption in the circuit. The conventional clock gating circuit is modified for connecting it with the EQSERL. This MCG circuit reduces unwanted power consumption. The conventional Wallace tree multiplier (WTM) involves full adder and half adder circuits. In this proposed work, a square root carry select adder (SQRT CSLA) with a reversible binary to excess-1 converter (BEC) and a ripple carry adder is presented. The reversible gates such as the Feynman gate, the Toffoli gate, and the dual key gate are employed. Finally, the proposed architecture is tested with different clocking circuits using Synopsys tools and the performance metrics like delay and power are observed.