Wafer Temperature Research Articles

Patterning of Sin and SiO2 Nanostructures for 3D Electronic Devices at Low Temperatures

Silicon oxide, SiO2, and silicon nitride, SiN, are widely used in memory and logic devices because of their dielectric properties, compatibility with silicon-based devices and etching selectivity. Advanced electronic devices are integrated increasingly in vertical direction, and critical etching challenges must be addressed to advance the technology roadmap. Among the enabling applications are vertical etching of SiO2 and SiN with high aspect ratio as well as lateral or isotropic etching of these films with high selectivity. Hydrofluoric acid gas has been used for over 30 years for isotropic etch of SiO2 (1, 2). The process has many similarities with wet etching using HF and requires the presence of water at the surface. Gas-phase etching of silicon nitride films has been demonstrated using moist HF vapor followed by heating of the wafer to remove ammonium fluorosilicate (NH4)2SiF6 or AFS as an intermediate reaction product (3). Recently, HF is used in high aspect ratio plasma etching of SiO2, SiN and multilayer stacks of these films at wafer temperatures below room temperatures (4). The elementary reactions bare resemblance with the vapor etch analogues. In this paper, we will present experimental results on plasma and vapor etching of SiO2 and SiN. The underlaying etching mechanisms will be explained using molecular dynamics and density functional theory.

Surface Kinetics and Uniformity Issues in Low-Temperature Epitaxy of Sige and Si:P Layers

Fabrication of the modern Si/SiGe-based devices normally necessitates the application of reduced temperatures (in the range about 550-750 °C) during the growth, which imposes significant kinetic limitations. As a result, the growth rate, layer composition, and dopant incorporation show high sensitivity to the process parameters and even small temperature non-uniformities over the wafer may result in considerable variation of the SiGe layer thickness and composition.In the growth of Si:P layers, the intrinsic Si growth kinetics is supplemented with the influence of the P concentration on the Si:P growth rate that may differ significantly as compared to the undoped Si despite P incorporation in concentrations of 0.1 % and even lower. In addition, the trend of the growth rate variation (increase or decrease) is different at the atmospheric and reduced operating pressures.Under all these inputs, control of the thickness and composition uniformity over the 300 mm wafer becomes challenging and should involve the adjustment of both temperature distribution and process parameters, including zonal distribution of the gas flow rates.To approach the solution of this problem, we have developed models of SiGe growth from SiH4/SiH2Cl2 (DCS) and GeH4 as well as Si:P growth from DCS and PH3 in the atmosphere of hydrogen with possible addition of HCl. The models account for high coverages of the surface with the adsorbed H2 and HCl, resulting in the growth limitation by low density of the free adsorption sites (kinetically limited growth mode). In case of SiGe, the model accounts also for the dependencies of surface kinetic parameters on the Ge concentration in the layer.The models were carefully verified using numerous experimental data on the layer growth rate and composition versus temperature and precursor flow rates. Calculations with the developed models reproduce the effect and facilitate interpretation of the following experimentally observed trends: higher growth rate and lower Ge concentration at elevated temperatures and the opposite tendency at a higher HCl supply. This behavior is explained in terms of stronger kinetic limitations for the Si part of the alloy that weaken with the temperature increase and contribution of the added HCl to the surface site blocking.The strong and non-monotonic dependence of Si:P growth rate on the PH3 supply is attributed to the competition between the adsorbed HCl and P-containing species. Addition of PH3 to the reactive gas mixture results, on the one hand, in additional coverage of the surface with these species but, on the other hand, in removal of the adsorbed HCl from the surface due to its interaction with these species, followed by the formation of volatile products.Next, the developed approaches have been applied to the detailed modeling of the process in widely used industrial reactors to address the uniformity issue in dependence of the operating parameters and reactor settings. In particular, variation of the uniformity for different temperature distributions over the wafer and gas injection parameters will be discussed. Also, conclusions are made on the relative sensitivity of the thickness and composition to possible non-uniformities of the wafer temperature and details of species transport inside the reactor. Figure 1

Numerical simulation and structural optimization of the diffusion furnace for crystal silicon solar cells

The diffusion furnace is an important device for crystalline silicon solar cell production. Given the rapid evolution of solar cell technology, large-scale, high-efficiency and mass-produced diffusion furnaces are required by the market. This puts forward higher requirements for the diffusion furnaces. In this study, a large-scale 3D model is established and validated by measured data in practical diffusion furnace. Its internal temperature, velocity and gas concentration fields are analyzed. The silicon wafer temperatures are found to be high at the top but low at the bottom. The temperature uniformity at both ends of silicon wafer groups is poor. To solve these problems, three structural optimization methods, namely the inlet pipe optimization, adding uniform-flow plates and the quartz boat optimization, are proposed and analyzed. The average mass fraction in the diffusion furnace is improved by 6.311% using the two-tube forked intake pipe. The uniform flow plates with evenly distributed pores on the lower half effectively improve the gas concentration uniformity on silicon wafer surfaces. The optimized quartz boat can improve the temperature uniformity of silicon wafers, though its deformation slightly increases by 0.338%. The silicon wafer temperature differences after quartz boat optimization are 13.77–50.27% smaller than those before optimization, which are conducive to reducing the thermal stress, the risk of thermal damage and the failure during manufacture and utilization of silicon wafers. Results in this study give guidelines for design and utilization of crystal silicon solar cell diffusion furnaces, some of which have been successfully used in Trina Solar Energy Co., China.

Numerical Analysis of Wafer Temperature with Respect to Radiation Variation in CVD Chamber

Numerical Analysis of Wafer Temperature with Respect to Radiation Variation in CVD Chamber

Infrared emission properties of VO2 films fabricated with different oxygen flow ratios

Infrared (IR) camouflage materials are widely used to realize thermal camouflage by adjusting the IR emissivity (ε) of the target object. However, ε modulation without an external energy supply is still a great challenge. Self-regulating VO2 films with different IR emission properties are investigated by adjusting the oxygen flow ratio (O2%) and film thickness. The ε of VO2 films changes before and after the phase transition, and the Δε (the difference of ε before and after the phase transition) of films is different under different O2%, and the maximum Δε can reach 0.49. In addition, the difference temperature (ΔTIR) between the actual temperature (TA: the surface temperature of a standard silicon wafer measured by IR camera, which represents the actual temperature of VO2 samples.) and the IR trapping temperature (TIR: the temperature of VO2 samples measured by IR camera.) is greater than 35 °C after the phase transition. With the range of 1.6 %–2.2 % O2, the IR emission transition temperature (Tε-MIT) and hysteretic width (ΔTε-MIT) increase with increasing O2%. The thickness of the VO2 film affects the IR emission characteristics. The VO2 film is suitable for thermal camouflage materials and for IR anticounterfeiting.

Effect of internal structure of a batch-processing wet-etch reactor on fluid flow and heat transfer

Batch-processing wet-etch reactors are the key equipment widely used in chip fabrication, and their performance is largely affected by the internal structure. This work develops a three-dimensional computational fluid dynamics (CFD) model considering heat generation of wet-etching reactions to investigate the fluid flow and heat transfer in the wet-etch reactor. The backflow is observed below and above the wafer region, as the flow resistance in this region is high. The temperature on the upper part of a wafer is higher due to the accumulation of reaction heat, and the average temperature of the side wafer is highest as its convective heat transfer is weakest. Narrowing the gap between wafer and reactor wall can force the etchant to flow in the wafer region and then facilitate the convective heat transfer, leading to better within-wafer and wafer-to-wafer etch uniformities. An inlet angle of 60° balances fluid by-pass and mechanical energy loss, and it yields the best temperature and etch uniformities. The batch with 25 wafers has much wider flow channels and much lower flow resistance compared with that with 50 wafers, and thus it shows better temperature and etch uniformities. These results and the CFD model should serve to guide the optimal design of batch-processing wet-etch reactors.

Synthesis of Plasmonically Active Titanium Nitride Using a Metallic Alloy Buffer Layer Strategy.

Titanium nitride (TiN) has emerged as a highly promising alternative to traditional plasmonic materials. This study focuses on the inclusion of a Cr90Ru10 buffer layer between the substrate and thin TiN film, which enables the use of cost-effective, amorphous technical substrates while preserving high film quality. We report best-in-class TiN thin films fabricated on fused silica wafers, achieving a maximum plasmonic figure of merit, -ϵ'/ϵ″, of approximately 2.8, even at a modest wafer temperature of around 300 °C. Furthermore, we delve into the characterization of TiN thin film quality and fabricated TiN triangular nanostructures, employing attenuated total reflectance and cathodoluminescence techniques to highlight their potential applications in surface plasmonics.

Quasiatomic layer etching of silicon nitride enhanced by low temperature

Plasma atomic layer etching is a dry etching process using a dose step to modify a material’s surface chemistry and an etch step to remove the modified surface layer. This method of etching has certain advantages over reactive ion etch due to its self-limiting etch process for highly controllable etch depth and reduced surface roughness. In this paper, we expand upon an anisotropic, plasma atomic layer etch recipe used to etch thin films of silicon nitride, which uses an H2 plasma to modify the surface layer of the material and an SF6 etch step to remove the modified surface. Several modifications are made to the recipe, including a reduction in the pressure during the SF6 step from 500 to 20 mT, to allow compatibility with modern inductively coupled plasma-reactive ion etch systems. We then explore this recipe at low wafer temperature and find a reduction of spontaneous isotropic SF6 etching. This results in an enhancement in the self-limiting aspect of the etch process, an improvement of the etched sidewall homogeneity, and a decrease in the etched surface roughness, which has the potential to be useful for reducing optical loss in silicon nitride waveguides and other nanoscale devices made in silicon nitride.

Plasma Ion Bombardment Induced Heat Flux on the Wafer Surface in Inductively Coupled Plasma Reactive Ion Etch

Plasma plays an important role in semiconductor processes. With the recent miniaturization and integration, the control of plasma became essential for success in the critical dimension of a few nanometers and etch narrow and deep holes with their high aspect ratios. Recently, the etching process has reached physical limitations due to a significant increase in wafer surface temperature under the elevated amount of RF power, affecting not only the warpage phenomenon, but also etching uniformity and etching profiles. Therefore, the plasma characteristics are identified using an invasive single Langmuir probe (SLP) for wafer temperature diagnosis. Optical data is obtained through a non-invasive optical emission spectroscopy (OES) and the plasma parameters are derived to compare and verify with the SLP. Two variables, electron temperature and electron density, are substituted for the heat flux formula to derive the heat flux according to the location. Using a wafer-type temperature sensor, the trends of the derived heat flux values towards wafer chuck were investigated. This study presents a method to calculate heat flux values in real time, anticipate wafer temperatures, and potentially illuminate existing ion heating problems.

Improvement of InGaP solar cells grown with TBP in planetary MOVPE reactor

In this study, the impact of various growth parameters, such as wafer temperature, device structures, and substrate misorientation, on the quality of InGaP epitaxial layers and solar cells grown in a planetary MOVPE reactor using TBP as a P source were investigated and optimized. Results showed that the carrier lifetime in unintentionally n-doped InGaP significantly decreased as the growth temperature increased from 560 to 590 °C. At temperatures above 600 °C, the growth of InGaP was unsuccessful due to extremely rough surface morphology. The study revealed that InGaP rear homojunction and rear heterojunction solar cells using n-type InGaP base layers displayed improved photo-carrier collection and performance compared to traditional front junction solar cells with p-type InGaP base layers. Notably, InGaP grown on GaAs (001) with a 5° miscut towards (111)A was found to have better quality, while InGaP grown on GaAs (001) with a 6° tilt towards (111)B had worse results in terms of carrier lifetime, PL intensity, and solar cell performance.

Wafer Temperature Control Using Helium Pressure and Observer-Based Model Predictive Control

Abstract Stabilizing a wafer’s temperature during plasma etching is a critical issue in semiconductor manufacturing. In this study, we propose feedback control of the wafer temperature using the pressure of helium gas (He) that is fed into the gap between the wafer and an electrostatic chuck (ESC) and an algorithm of the model predictive control (MPC) combined with an observer. The temperatures are measured only at the wafer edge zone and the ESC ceramic plate that are accessible during the process. The observer estimates wafer temperatures of center and edge zones and the injected heat power with the help of the measured edge zone temperature. The MPC determines the optimal He pressures based on the estimated temperatures to control both zone temperatures. The algorithm of the feedback control was formulated, and its validity was experimentally confirmed. Results showed that the observer worked well to estimate both zone wafer temperatures and the injected heat power. Results also showed that the temperatures were successfully controlled.

Heat-transfer modeling of the gas gap under a wafer

The wafer temperature is a critical observable in semiconductor manufacturing. One of the various mechanisms determining this temperature is the heat transfer in a gas gap between the wafer and the electrostatic chuck (ESC). Various correlations for this heat transfer are available. However, to calculate more accurately the spatial distribution of this temperature, computing the flow in this gap is necessary. With this motivation in mind, this paper presents a computational fluid dynamics model (CFD) for the flow in the wafer-ESC gap that is designed to be easy to implement in industrial CFD codes. This model is tested in various channel-flow problems and then applied to a generic wafer-ESC configuration. For this configuration, CFD results show that varying the flow rate split between three zones, or the total flow rate, or the rugosity of the wafer affect the heat transfer coefficient and its spatial variation. This is important since controlling this variation would allow to maintain a uniform wafer temperature. The model could be used in more realistic wafer-ESC configurations to consider many other parameter variations, such as the size of injection holes, a radially varying gap distance, or the use of many injection zones. From a broader viewpoint, the model is applicable to vacuum problems other than the wafer-ESC configuration.

Heat transfer mechanism of electrostatic chuck surface and wafer backside to improve wafer temperature uniformity

Semiconductor manufacturing technology keeps toward scaling down to a few nanometers. To protect the process yield and achieve the success of chip manufacturing, the center-to-edge uniformity of the wafer's temperature has become a crucial parameter. The thermal characteristics of the wafer are dominantly affected by the electrostatic chuck, which is generally used to support the wafer in the manufacturing process. In particular, the backside gas, which passes through the interface between the wafer and electrostatic chuck, is important for cooling the wafer below a critical temperature. The heat transfer via a backside gas can be explained by the layer-bulk model, and its pressure is a key factor to determine the cooling effectiveness. In this paper, a one-dimensional thermal circuit model is established for a system including the wafer, electrostatic chuck, and backside gas to calculate the convective heat transfer coefficient caused by the backside gas. The numerical results showed that the uniformity of the wafer's temperature became worse as the backside gas pressure increased in a low-pressure range but significantly improved above a critical value of the gas pressure. Based on our findings, we concluded that the backside gas pressure should be optimized to improve the uniformity of the wafer temperature.

Computational fluid dynamics modeling of a wafer etch temperature control system

Next-generation etching processes for semiconductor manufacturing exploit the potential of a variety of operating conditions, including cryogenic conditions at which high etch rates of silicon and very low etch rates of the photoresist are achieved. Thus, tight control of wafer temperature must be maintained. However, large and fast changes in the operating conditions make the wafer temperature control very challenging to be performed using typical etch cooling systems. The selection and evaluation of control tunings, material, and operating costs must be considered for next-generation etching processes under different operating strategies. These evaluations can be performed using digital twin environments (which we define in this paper to be a model that captures the major characteristics expected of a typical industrial process). Motivated by this, this project discusses the development of a computational fluid dynamics (CFD) model of a wafer temperature control (WTC) system that we will refer to as a “digital twin” due to its ability to capture major characteristics of typical wafer temperature control processes. The steps to develop the digital twin using the fluid simulation software ANSYS Fluent are described. Mesh and time independence tests are performed with a subsequent benchmark of the proposed ANSYS model with etch cooling system responses that meet expectations of a typical industrial cooling system. In addition, to quickly test different operating strategies, we propose a reduced-order model in Python based on ANSYS simulation data that is much faster to simulate than the ANSYS model itself. The reduced-order model captures the major features of the WTC system demonstrated in the CFD simulation results. Once the operating strategy is selected, this could be implemented in the digital twin using ANSYS to view flow and temperature profiles in depth.

A TCAD study on the effect of process parameters on silicon optical phase shifter performance

On-chip integrated optical phase shifters are an important part of optical phase modulators. The performance of such modulators relies heavily on the phase shifter performance, which in turn depends on multiple process parameters. This paper reports the study of the effect of different process parameters on the performance of a silicon PN optical phase shifter obtained by process simulation using Silvaco® TCAD. The effect of dopant implantation dose, implantation energy, annealing temperature and time, wafer temperature, wafer tilt and rotation, and pre-amorphization on the phase and absorption of light is discussed. The 3-dB modulation bandwidth of a lumped phase shifter and the dependency of the performance metrics on different process parameters are presented. Monte Carlo numerical simulation shows that the free-carrier absorption has a much greater dependency on the process parameters than the phase shift. The study shows that ion channeling poses a limiting factor on the phase shifter performance, which can be improved by tilting the wafer or using a pre-amorphized substrate for implantation. The study shows that the 3-dB modulation bandwidth is highly dependent on the wafer tilt angle, rotation angle, and the lattice structure of the solid substrate. A bandwidth improvement of more than 5× is observed with 1.7× lower absorption for a pre-amorphized sample at −5 V compared to a crystalline sample with the same process flow.

Probe card-Type multizone electrostatic chuck inspection system

Electrostatic chucks (ESCs) are major components of the equipment used to improve the production yield of wafers and temperature uniformity across wafer surfaces by controlling the wafer temperature precisely. However, ESCs are directly exposed to harsh environments, such as plasma, chemical gases, and high temperature fluctuations. Therefore, ESCs may malfunction if used for a certain period. Therefore, repair and performance verification of failed ESCs are required. In this study, we developed a multizone probe card system suitable for electrical testing of the heating electrodes embedded in ESC control modules to correlate the failure mode factors of ESCs. This system has the advantages of examining the resistance of the internal heating electrode of a 144-zone ESC in a short time and detecting an abnormality in this component based on the measured data. The heating electrode resistance measurement error rate of the developed system was 1%, and the maintenance time was reduced by approximately 66% compared with that of existing ESC maintenance methods.

Dry etching in the presence of physisorption of neutrals at lower temperatures

In this article, we give an overview about the chemical and physical processes that play a role in etching at lower wafer temperatures. Conventionally, plasma etching processes rely on the formation of radicals, which readily chemisorb at the surface. Molecules adsorb via physisorption at low temperatures, but they lack enough energy to overcome the energy barrier for a chemical reaction. The density of radicals in a typical plasma used in semiconductor manufacturing is one to two orders of magnitude lower than the concentration of the neutrals. Physisorption of neutrals at low temperatures, therefore, increases the neutral concentration on the surface meaningfully and contributes to etching if they are chemically activated. The transport of neutrals in high aspect ratio features is enhanced at low temperatures because physisorbed species are mobile. The temperature window of low temperature etching is bracketed at the low end by condensation including capillary effects and diminished physisorption at the high end. The useful temperature window is chemistry dependent. Besides illuminating the fundamental effects, which make low temperature processing unique, this article illustrates its utility for semiconductor etching applications.

Impact of organic particles from wafer handling equipment on silicon heterojunction pseudo-efficiency

Within this paper a systematic analysis of particle transfer onto SHJ Solar cell precursors by handling with suction cups and the impact on the pseudo efficiency is presented. The study establishes a correlation between particle area coverage and a resulting loss of pseudo solar cell parameters. The analysis was carried out on one hand by means of SEM measurements at the contact points between suction cup and wafer to quantify particle transfer and on the other hand by means of suns photoluminescence imaging measurements to evaluate the resulting losses. It is shown that the choice of contact material and the wafer temperature have a significant influence on the transferred particle number, their size and the resulting particle area coverage. A local electrical defect was observed at these particle-rich spots, which also affected a larger area around this insufficiently passivated region. This had a significant negative effect on the pseudo efficiency, which is more pronounced for increasing particle area coverage. If the particle density is increased by 0.1% within an area of 800 mm2, the pseudo efficiency in this area decreases by almost 1.2%Relative. The correlation found can be used to predict an efficiency loss using standard photoluminescence images.

New ECR source ion implanter with advanced wafer temperature control for material modification

New ECR source ion implanter with advanced wafer temperature control for material modification

Improved Ferroelectric Properties in Hf0.5Zr0.5O2 Thin Films by Microwave Annealing.

In the doped hafnia(HfO2)-based films, crystallization annealing is indispensable in forming ferroelectric phases. In this paper, we investigate the annealing effects of TiN/Hf0.5Zr0.5O2/TiN metal-ferroelectric-metal (MFM) capacitors by comparing microwave annealing (MWA) and rapid thermal annealing (RTA) at the same wafer temperature of 500 °C. The twofold remanent polarization (2Pr) of the MWA device is 63 µC/cm2, surpassing that of the RTA device (40 µC/cm2). Furthermore, the wake-up effect is substantially inhibited in the MWA device. The orthorhombic crystalline phase is observed in the annealed HZO films in the MWA and RTA devices, with a reduced TiN and HZO interdiffusion in MWA devices. Moreover, the MFM capacitors subjected to MWA treatment exhibit a lower leakage current, indicating a decreased defect density. This investigation shows the potential of MWA for application in ferroelectric technology due to the improvement in remanent polarization, wake-up effect, and leakage current.