Wafer Level Packaging Research Articles

Synthesized Improvement of Die Fly and Die Shift Concerning the Wafer Molding Process for Ultrafine SAW Filter FOWLP

As the surface acoustic wave (SAW) filters incline to ultrafine, the failures resulting from the wafer molding process have become increasingly prominent. A methodology for coupling the mechanisms of die fly and die shift for the SAW filter miniatured with 737 μm × 517 μm × 200 μm is developed for the trade-off between reliability and yields. In terms of die fly and die shift, the former occurs before the epoxy molding compound (EMC) is cured in the temperature rise period, while the latter occurs in the cooling stage after being cured. The die fly is induced by the fluid flow force in the high-temperature stage of heat compression, which is fatal for the scrap. Followed by the cooling stage, the CTE (coefficient of thermal expansion) misalignment between the die and epoxy molding compound (EMC) seriously affects the die shift and the following lithography process yields. The debonding critical energy in the mixed mode is employed to avert the die fly. Then, the die fly can be shunned by fine-tuning the die thickness, die layout, and EMC layout. A methodology to measure die shift was conducted, by which a total of 47,568 dies were embedded using compression molding. The mechanical error of the mounter and the die shift law are comprehensively leveraged, indicating that the die shift can be controlled within 50 μm for 8-inch wafer-level packaging.

Exploring the Influence of Material Properties of Epoxy Molding Compound on Wafer Warpage in Fan-Out Wafer-Level Packaging.

This study investigated the impact of material properties of epoxy molding compounds on wafer warpage in fan-out wafer-level packaging. As there is currently a lack of comprehensive discussion on the various material property parameters of EMC materials, it is essential to identify the critical influencing factors and quantify the effects of each parameter on wafer warpage. The material properties include Young's modulus of the epoxy molding compound before and after the glass transition temperature (Tg) range of 25-35 °C (EL) and 235-260 °C (EH), coefficient of thermal expansion (α1, α2), and the temperature change (∆T) between EL and EH. Results show that, within the range of extreme values of material properties, EL and α1 are the critical factors that affect wafer warpage during the decarrier process in fan-out packaging. α1 has a more significant impact on wafer warpage compared with EL. EH, α2, Tg, and ∆T have little influence on wafer warpage. Additionally, the study identified the optimized material property of the epoxy molding compound that can reduce the maximum wafer warpage in the X and Y directions from initial values of 7.34 mm and 7.189 mm to 0.545 mm and 0.45 mm, respectively, resulting in a reduction of wafer warpage of 92.58% (X direction) and 93.74% (Y direction). Thus, this study proposes an approach for evaluating the impact of material properties of epoxy molding compounds on wafer warpage in fan-out wafer-level packaging. The approach aims to address the issue of excessive wafer warpage due to material variation and to provide criteria for selecting appropriate epoxy molding compounds to enhance process yield in packaging production lines.

Chemical and Morphological Modifications Induced by Argon Plasma Treatments on Fluorinated Polybenzoxazole Films.

Fluorinated photodefinable polymers are widely employed as re-distribution layers in wafer-level packaging to produce microelectronic devices because of their suitable low dielectric constant and moisture absorption, high mechanical toughness, thermal conductivity and stability, and chemical inertness. Typically, fluorinated photodefinable polybenzoxazoles (F-PBOs) are the most used in this field. In the present work, we investigated by atomic force microscopy, X-ray photoelectron spectroscopy, and Fourier transform infrared spectroscopy the morphological and chemical modifications induced by Ar plasma treatments on F-PBO films. This process, used to remove surface contaminant species, as well as increase the polymeric surface roughness, to improve the adhesion to the other components during electronic packaging, is a crucial step during the manufacturing of some microelectronic devices. We found that argon plasma treatments determine the wanted drastic increase of the polymer surface roughness but, in the presence of a patterned silver layer on F-PBO, needed for the fabrication of electric contacts in microelectronic devices, also induce some unwanted formation of silver fluoride species.

A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station

This article demonstrates a 39-GHz CMOS phased-array beamformer aiming for power-efficient and area-efficient fifth-generation (5G) dual-polarized multiple-in–multiple-out (DP-MIMO) applications. To address the digital pre-distortion (DPD) implementation issue in the massive beamformer elements with Doherty technique integrated, an inter-element mismatch compensation technique is introduced for improving the shared-lookup table (LUT) DPD performance over the process, voltage and temperature (PVT) variations. A bidirectional Doherty power amplifier (PA)-LNA is proposed to enhance the power back-off (PBO) efficiency regarding the high peak-to-average power ratio (PAPR) 5G signals, meanwhile cost down the system by the unbalanced neutralized bidirectional operation. The proposed phased-array beamformer chip is fabricated in 65-nm CMOS technology and packaged in a wafer-level chip-scale package (WLCSP). Each element occupies only a 0.82-mm2 chip area, including the on-chip low-dropout regulator (LDO). The measured stand-alone Doherty PA-LNA achieves 18.9-dBm saturated output power with 17.8% power-added efficiency (PAE) at 6-dB PBO in PA mode and obtains a 4.8-dB noise figure (NF) at 40 GHz in LNA mode. By utilizing the proposed mismatch compensation, the measured 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiple access (OFDMA)-mode error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) with the shared-LUT DPD are improved from −22.4 to −25.0 dB and from −28.7 to −32.1 dBc, respectively. The 64-element module achieves a 55.2-dBm saturated effective isotropic radiated power (EIRP) and supports 21-Gb/s single-carrier (SC) mode data streaming. The measured 64-element transmitter (TX) EVM is −25.2 dB at 43.2 dBm with 3.5-GSymbol/s baud rate in 64 QAM, and the corresponding 64-to-4 elements TX-to-receiver (RX) EVM is −22.5 dB. The consumed power for each element is 402 mW at saturation output point in TX mode and 87 mW in RX mode.

On the optimization of molding warpage for wafer-level glass interposer packaging

On the optimization of molding warpage for wafer-level glass interposer packaging

High Gain and Wideband Antenna-in-Package Solution Using Fan-Out Technology

AbstractThe technology of fan-out wafer level packaging (FOWLP) has been widely adopted for millimeter wave antenna-in-package (AiP) system integration with low interconnection parasitic parameters. Present AiP solutions using FOWLP technology generally form antenna pattern on redistribution layer, which brings design inconvenience. In our work, a low-cost printed circuit board RO4350B laminate for substrate-integrated waveguide (SIW) antenna with a relatively large size is integrated, forms a three-dimensional stacked structure. The AiP employs a right-angle transition board embedded in epoxy molding compound (EMC), which transmits millimeter-wave signal to the SIW antenna stacked on the backside of EMC. The SIW antenna consists of 4 × 4 radiation slots with modified magneto-electric dipole for bandwidth enhancement. The measured gain is 14dBi at 60 GHz with bandwidth beyond 55–65 GHz. The three-dimensional AiP structure improves heat dissipation, no extra thermal design is needed for applications under 0.5 W mm-wave chip power consumption. The AiP module is manufactured and measured on the test board. The proposed approach is a convenient solution for wide band and high gain millimeter wave AiP system integration.

Room-temperature bonding of Al2O3 thin films deposited using atomic layer deposition

In this study, room-temperature wafer bonding of Al2O3 thin films on Si thermal oxide wafers, which were deposited using atomic layer deposition (ALD), was realized using the surface-activated bonding (SAB) method. Transmission electron microscopy (TEM) observations indicated that these room-temperature-bonded Al2O3 thin films appeared to work well as nanoadhesives that formed strong bond between thermally oxidized Si films. The perfect dicing of the bonded wafer into dimensions of 0.5 mm × 0.5 mm was successful, and the surface energy, which is indicative of the bond strength, was estimated to be approximately 1.5 J/m2. These results indicate that strong bonds can be formed, which may be sufficient for device applications. In addition, the applicability of different Al2O3 microstructures in the SAB method was investigated, and the effectiveness of applying ALD Al2O3 was experimentally verified. This successful SAB of Al2O3 thin films, which is a promising insulator material, opens the possibility of future room-temperature heterogenous integration and wafer-level packaging.

Development and Characterization of Low Temperature Wafer-Level Vacuum Packaging Using Cu-Sn Bonding and Nanomultilayer Getter.

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications.

Research on Defect Inspection Technology for Bump Height in Wafer-Level Packaging Based on the Triangulation Method

With the advent of the era of big data and the vigorous development of consumer electronics, the demand for higher-speed processing capacity for gigantic amounts of data is increasing; this requires finer and far more numerous connections between dies as an essential component for connection and electronic communication between layers. The coplanarity of the height of micro bumps is crucial to ensure the reliability of the chip. The triangulation method has been widely used in various types of visual inspection applications over the past several years due to its high measurement accuracy and fast detection speed. In this paper, the application of triangulation technology is analyzed and used in micro bump height measurement. The measurement system proposed consists of a delicate design, a linearly arranged light projection module and a high-quality imaging module. Along the light stripe, multiple-height data of micro bumps are collected in a frame, and the full-field measurement is realized as the wafer is driven by the high-precision motional stage, following the optimal measurement route planned previously. In the scanning process, the images of the light strip projected on the top and bottom of the micro bumps are simultaneously acquired by the sophisticated micro vision system, and then the heights of micro bumps are calculated from a simple formula based on the geometry of the specimen and the system configuration. The experimental results demonstrate that the measuring deviation of the micro bump height has an accuracy of 1.5 μm.

Wafer-level packaging solder joint reliability lifecycle prediction using SVR-based machine learning algorithm

Abstract The development of new electronic packaging structures often involves a design-on-simulation approach. However, simulation results can be subjective, and there can be variances in outcomes depending on who is conducting the simulation. To address this issue, packaging designers are now turning to machine learning to increase the accuracy and efficiency of the design process. This research study focuses on using support vector regression (SVR) techniques, such as single kernel, multiple kernels and a new SVR technique, to predict the reliability of the wafer-level packaging (WLP). By doing so, the study aims to provide designers with a reliable way to assess the reliability life cycle of their packaging designs. This research includes three steps: validating the WLP's reliability using finite element analysis (FEA) and experiment results, using the validated FEA result as input to obtain a predictive model through the SVR technique and the evaluating predictive model's performance. The results show that the predictive models developed using the SVR technique have stable performance on different testing data, which is consistent with the FEA results.

A K-Band Hybrid-Packaged Temperature-Compensated Phased-Array Receiver and Integrated Antenna Array

This article presents an eight-channel 1.9-dB noise figure (NF) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band phased-array receiver (RX) for satellite communication (SATCOM). It employs the hybrid-packaged 65-nm CMOS beamformer and 0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs low-noise amplifiers (LNAs) based on the fan-out wafer-level chip-scale packaging (WLCSP) technology. For the power-efficient RX implementation, the power consumption of gain and phase tuning blocks is discussed, and the fully passive phase shifter (PS) and attenuator (ATT) are employed in this work. A global biasing scheme is proposed to ensure performance uniformity across temperature variations. Across the SATCOM band of 17.7–20.2 GHz, the proposed hybrid-packaged phased-array RX IC only consumes 30.2-mW dc power per channel and achieves < 1.2-dB gain variation and < 0.9-dB NF variation from −40° to 85 °C. Based on the RX IC, a dual-polarized 1024-element RX antenna array is further introduced. The measured gain-to-noise temperature ratios (G/Ts) are 6.22 and 6.51 dB/K at 19.7 GHz for left- and right-hand circular polarizations, respectively.

Fabrication of Tri-Axial MEMS Tactile Sensor for Minimally Invasive Medical Application using Wafer-Level Packaging

Fabrication of Tri-Axial MEMS Tactile Sensor for Minimally Invasive Medical Application using Wafer-Level Packaging

Polyimides with low dielectric constants and dissipation factors at high frequency derived from novel aromatic diamines with bistrifluoromethyl pendant groups

Fan-out wafer-level packaging (FOWLP) urgently demands low dielectric constant and dissipation factor interlayer dielectric materials to mitigate high transmission losses at high frequencies.

Ultrathin Glass-Based Wafer-Level Integration for Miniaturized Hermetic MEMS Application

In this article, a glass-based hermetic structure has been packaged at wafer level with a thickness thinner than 200 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> and a size smaller than 1 mm2, showing the prospective way to realize the miniaturization of microelectromechanical systems (MEMS) with high throughput. For the development of this novel wafer-level packaging platform, material selection of metal wire was studied. Next, the technique of metal patterning on the cavity structure was demonstrated for the fabrication of seal ring and electrical connection simultaneously. At last, the ultrathin hermetic structure was sealed by metal-to-metal bonding at wafer level. These technologies can be widely used in advanced miniaturized packaging applications for next-generation electronic components.

Design of a Packaged Multi-radius Multi-path Solenoidal Inductor for Redistribution Layers

This paper proposes a three-dimensional solenoidal inductor using a “multi-radius multi-path” (MRMP) structure that targets integrated voltage regulators (IVRs). Multi-radius (MR) refers to the inclusion of additional turns inside the solenoid, and multi-path (MP) describes the division of a single metal into two paths to reduce non-uniformity in currents due to differences in length. Using an MRMP structure, we propose two new inductor designs for fan-out wafer-level packaging. A two-layer MRMP approach that implements the multi-path in an additional layer, and a one-layer MRMP configuration avoids the need for an additional layer by incorporating the multi-path in an inner turn. We compare inductance and quality performance according to the frequency of the two designs. When the MR technique is applied, the inductance increases due to the increase in the length of the inductor, but resistance also increases. As the frequency increases, alternating current (AC) resistance becomes dominant. The MP increases the quality factor by alleviating skin and proximity effects, which are the main causes of increased AC resistance. Analytical modeling is carried to rapidly estimate and optimize direct current inductance using partial inductance. To verify the improvement in efficiency due to the proposed inductor structure, we propose a prototype IVR that includes inductor loss and investigate the efficiency with circuit simulations using an IVR design with a conversion ratio of 3.6 V:1.8 V operating at 10 MHz. By using the two-layer MRMP inductor, the prototype IVR efficiency increases from 72.6% to 82.1%. A one-layer MRMP inductor, an IVR design with conversion ratio of 1.8 V:1.0 V and an operating frequency of 40 MHz, increases the maximum efficiency from 56.6% to 75.1%.

Design Optimization by Virtual Prototyping Using Numerical Simulation to Ensure Thermomechanical Reliability in the Assembly and Interconnection of Electronic Assemblies

Abstract A methodology is presented that allows the evaluation of the thermomechanical reliability of electronic packages using “virtual prototyping.” Here, a virtual flip chip ball grid array (FC-BGA) is examined in comparison to a reference chip scale package (CSP). The comparison is performed using finite element simulation. A combined measurement-simulation technique is used to calibrate the finite element simulations on a reference object. The adjustment is based on the in-plane deformation field obtained by both simulation and optical measurement. For the latter, an optical sensor is used for in-plane deformation and strain field analysis based on the gray-scale correlation method. The findings obtained can be extrapolated to alternative package types with different but similar design to evaluate their suitability for the desired application before physical fabrication.

Novel Temporary Bonding/Debonding System Enabling Advanced Packaging Process

Novel temporary bonding/debonding system including high heat resistant temporary bonding adhesive and debonding methods with conventional laser ablation or newly developed photonic release by Xe flash light irradiation will be introduced. Our new temporary bonding adhesive shows no delamination and no voiding after thermal treatment over 300 ℃ and can be easily removed by peeling off after debonding from the support carrier. In addition, by adopting the dual layer structure with adhesive layer and laser release layer, we can form the suitable structure for debonding with laser ablation. Furthermore, in the case that metal layer is applied instead of laser release layer, debonding by one-shot Xe flash light irradiation within 5 ms can be achieved, indicating the increased throughput at debonding process as compared to the other dobonding methods. Process demonstration results of wafer thinning down to 50 μm, fan-out wafer level packaging (FOWLP) will also be shown in this paper.

Wafer level hermetic bonding and packaging using recrystallized parylene

This work reports a wafer-level vacuum packaging technique for microelectromechanical system (MEMS) using recrystallized parylene material as a bonding layer. The effect of thermal annealing on the crystallinity of the parylene surface was demonstrated. The low-temperature, stable, homogeneous, and defect-free recrystallized parylene is found as an excellent bonding material for hermetic packages, suitable for the packaging of MEMS sensors. The material’s recrystallization improves its capabilities as a moisture and air barrier. The mechanical stability of the bond interface was also investigated by measuring the package’s tensile and shear strength. In the absence of a vacuum bonding tool, a Ti getter was integrated into the cavity of the glass capping wafer to create the vacuum and test the hermeticity. The MEMS silicon Pirani gauge was used to monitor the pressure changes inside the sealed cavity. After the getter activation, it was observed that there was a decrease in the pressure from atmospheric pressure to 0.2 mbar for the first few days; after that, no noticeable change was observed. The hermeticity of the packaged device was examined, and the vacuum level inside the package remained the same for the last 70 d. The recrystallized parylene bonded micro package shows better hermeticity than the non-recrystallized parylene micro package.

Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures

The integrated fan-out (InFO) wafer-level chip-scale package (WLCSP) is introduced for modern system-in-package designs with larger I/O counts, higher interconnection density, and small form factors. A redistribution layer (RDL) in an InFO package is an extra metal layer for interchip connections, and RDL routing is crucial for achieving desired interchip connections. In a high-density InFO package, multiple RDLs with flexible vias are often adopted. To integrate chips of different technology nodes into one package, irregular pad structures need to be considered; however, no published RDL routing work considers flexible vias or irregular pad structures. This article formulates a new RDL routing problem with unified-assigned pad pairs on a via-based multilayer multichip InFO package with irregular pad structures and presents the first algorithm for this problem. The algorithm consists of a preprocessing stage, three routing stages, and a layout optimization stage. The preprocessing stage analyzes routing resources and potential routing congestion. The first routing stage performs layer assignment based on a weighted maximum planar subset of chords algorithm to route interchip nets concurrently. The second routing stage constructs a 3-D routing graph based on partitioned octagonal tiles to handle the irregular layout structure and applies A*-search to route remaining interchip nets. The third routing stage transforms a routing graph into a network-flow model to perform concurrent routing for chip-to-board nets by applying the minimum-cost maximum-flow algorithm. Finally, we develop an efficient linear-programming-based layout optimization algorithm to find desired solutions. Experimental results show that our router can achieve 100% routablility for all benchmarks under limited RDLs, while the previous state-of-the-art work cannot.

Enhancing Optical Performance of Chip-Scale Packaged White LEDs by Phosphor-in-Glass With High-Reflective Dam

In this work, the optical performance of chip-scale packaged (CSP) white light-emitting diodes (LEDs) was enhanced by a phosphor-in-glass (PiG) converter with a high-reflective dam. The high-reflective dam consisted of boron nitride (BN)/silicone composite fabricated at the side wall of the LED chip and PiG converter to obtain the PiG-BN-CSP LED. The optical performance of PiG-BN-CSP LED was optimized by adjusting the concentration of BN particles. When the BN concentration is 7.5 wt%, the PiG-7.5BN-CSP LED achieves an appropriate natural white light. The related luminous efficiency (LE), correlated color temperature (CCT), and chromaticity coordinate are 104.7 lm/W, 5714 K, and (0.3273, 0.3563), respectively. The beam angle of PiG-BN-CSP LED is effectively controlled by adjusting the BN concentration. The beam angle of 118.5° is achieved at the BN concentration of 7.5 wt%. The maximum temperature of PiG-7.5BN-CSP LED is 92.7 °C when the input current is 1200 mA. Furthermore, the PiG-up BN-CSP achieves better optical performance compared with the PiG-up-CSP. The results show that the PiG with a high-reflective dam is an efficient CSP structure for high-power-density white LEDs.