Wafer Heating Research Articles

Balanced truncation model reduction for laser heating wafer model in frequency restricted domain

Modeling and simulating laser heating phenomena are crucial for optimizing manufacturing processes and ensuring high-quality final products. A major challenge in semiconductor manufacturing is achieving accurate, real-time temperature control during wafer heating. To reduce the computational burden of complex mathematical models, low-dimensional reduced models can be employed. In this paper, we develop a mathematical model for laser heating in silicon wafers. For model reduction, we use the balanced truncation method, considering both frequency-unrestricted and restricted cases. Additionally, the rational Krylov subspace method is applied to solve high-dimensional sparse matrix equations. To gain key physical insights, we use the COMSOL Multiphysics package. Finally, some numerical experiments are conducted using MATLAB to validate the proposed approach.

Wafer heating uniformity: enhancement using toroidal slot antennas and resonant cavity modes

Wafer heating uniformity: enhancement using toroidal slot antennas and resonant cavity modes

Temperature control of electric hotplate based on Smith fuzzy multi-level integral separation PID

In order to improve the processing yield of large-size wafers, the partition control method of silicon carbide wafer heating plate heated by metal oxide conductive coating is studied, and a 4-partition temperature control system based on Smith fuzzy multilevel integral separation PID is proposed so as to solve the surface temperature consistency of the wafer heating plate under the requirement of high precision. Through the thermal effect simulation to establish the system model, the heat distribution in each region is analyzed. And then the heating plate temperature control system based on PLC controller is built, and Smith fuzzy multilevel integral separation PID algorithm to facilitate the practical application to improve the control accuracy is proposed, combined with the system model and the conventional PID algorithm in MATLAB for comparison. Finally the experimental verification is carried out based on the established heating plate temperature control system. Simulation and experimental results show that the present control method has a higher control accuracy, and can realize the consistency of the surface temperature of the heating plate stabilized at about 0.05℃, the average temperature steady-state error ±0.05℃, and the control effect is good.

마이크로웨이브 캐비티 모드 전환에 의한 웨이퍼 가열 특성

As a solution to the limitations of semiconductor miniaturization and multilayer technology, Atomic Layer Deposition(ALD) and Atomic Layer Etching(ALE) technologies are attracting attentions. For ALD and ALE process technologies, temperature uniformity is an important factor in determining the film quality of thin films and aspect ratio. Conventionally, an indirect heating method by a buried heater that heats the substrate is used, but the method has a decrease in productivity due to the preheating process. This study introduce a direct wafer heating method using GHz band microwaves to suggest the direction for new heater equipment to solve the problems of the existing method. At atmospheric pressure, the 2.45 GHz microwave is radiated through a double-slot antenna to heat a 12inch silicon wafer. The microwave propagates through the waveguide in TE10 mode and heats the wafer by cavity heating. It was confirmed through simulations and experiments that the wafer can be heated quickly using microwaves and the temperature distribution can be made uniform by the cavity conversion.

The method of images in thermoelasticity with an application to wafer heating

The well-known method of images relates the solution of the heat equation on (typically n = 2 or n = 3) to the solution of the heat equation on certain spatial subdomains Ω of By reformulating the method of images in terms of a convolution kernel, two novel extensions are obtained in this paper. First, the method of images is extended from thermal problems to thermoelastic problems, that is, it is demonstrated how the heat-induced deformations on can be related to the heat-induced deformations on certain subdomains Ω of Secondly, an explicit expression for the convolution kernel for the disk is obtained. This enables the application of the method of images to circular domains to which it could not be applied before. The two obtained extensions lead to a computationally efficient simulation method for repetitive heat loads on a disk. In a representative simulation example of wafer heating, the proposed method is more than ten times faster than a conventional Finite Element approach.

Performance-Based Active Wafer Clamp Design for Wafer Heating Effects in EUV Lithography

To improve overlay and focus errors in lithographic applications, an active wafer clamp (AWC) concept is proposed. Using this concept, mechanical actuators deform the wafer to compensate thermally induced deformations. In [1] a localized feedforward (FF) control algorithm for the AWC concept was introduced. In this paper we aim to improve this algorithm and discuss practical implications for the design of an AWC concept, motivated by the optimal performance that can be achieved using the FF control scheme. This leads to a design, where the actuators are placed below the clamping electrode, and 3-degree-of-freedom (DOF) actuators can be reduced to 2-DOF actuators with negligible performance loss. Considering the fact that the AWC concept contains tens of thousands of actuators, this leads to a significant reduction. Finally, other methods are presented to further reduce the computational complexity to control the AWC.

Optimal Thermal Actuation for Mitigation of Heat-Induced Wafer Deformation

An important step in the production of integrated circuits is the projection of the pattern of electronic connections on a silicon wafer. The light used to project the pattern moves over the wafer and induces a local temperature increase. The resulting thermal expansion of the wafer leads to a significant reduction in the imaging quality of next-generation wafer scanners. Thermal actuators that move together with the projection light can be used to improve the imaging quality. Because the placement of these actuators largely determines the performance of the resulting control system, a method to support the design of an effective thermal actuator layout is presented. The proposed method computes the smallest actuation heat load that consists of a single spatial shape and respects certain constraints on wafer deformations. A gradient-based optimization algorithm is presented to compute the optimal actuation heat load. The proposed method is applied to a wafer heating problem for which the resulting shapes of the actuation heat load have a clear physical interpretation.

A Distributed-Parameter Approach for the Surface Temperature Estimation of an LED Heated Silicon Wafer

A variety of processes in the semiconductor industry require heating of the silicon wafer to the desired temperature. This process is widely referred to as rapid thermal processing. However, the contactless measurement of the surface temperature of the wafer is still a major challenge, especially in the case of rotating wafers. Measurements using infrared cameras are not suitable due to the fact that silicon is transparent in this wavelength range. Special sensors based on the principle of pyrometry are available, but such sensors can only measure the surface temperature at one single point. This paper presents an observer approach that estimates the wafer’s surface temperature by using the temperature measurement of only one pyrometer. The approach is based on a mathematical model capturing the dynamical behavior of the wafer’s temperature. It relies mainly on the quasi-linear heat equation. Real world experiments demonstrate the achieved accuracy of the proposed approach.

Semi-analytic approximation of the temperature field resulting from moving heat loads

Moving heat load problems appear in many manufacturing processes, such as lithography, welding, grinding, and additive manufacturing. The simulation of moving heat load problems by the finite-element method poses several numerical challenges, which may lead to time consuming computations. In this paper, we propose a 2D semi-analytic model in which the problem in two spatial dimensions is decoupled into three problems in one spatial dimension. This decoupling significantly reduces the computational time, but also introduces an additional error. The method is applied to a wafer heating example, in which the computational time is reduced by a factor 10 at the cost of a 4% error in the temperature field.

Mechanism behind dry etching of Si assisted by pulsed visible laser

Poly-Si films were etched using a 13.56 MHz capacitively coupled plasma source while simultaneously being exposed to a pulsed Nd:YAG laser using 266 and 532 nm lines, with Gaussian pulse durations of 100 Hz and 7 ns. For a fluorocarbon etch recipe of 50:8 sccm Ar:C4F8 with varying O2, a minimum laser intensity for the etch onset was necessary to overcome CFx polymer deposition. This etch onset occurred at 6 ± 1 mJ/cm2/pulse; beyond this onset, the etch rate increased linearly with laser intensity. Null results of laser etch enhancement using continuous wave diode sources demonstrated the necessity of the instantaneous application of the pulsed Nd:YAG source. To determine the mechanism of laser etch enhancement at 532 nm, highly doped Si samples were tested, with varying optical absorption depths while keeping the photon energy constant. It was shown that at phosphorus contents of 1019 cm−3 and 1021 cm−3, 532 nm etch enhancement trends were 1.7× and 3.7× higher than those on intrinsic Si, showing that instantaneous surface heating was key in desorbing involatile etch products. Further investigation of the surface fluorine content via X-ray photon spectroscopy showed that distinct desorption stages occurred for increasing pulse energy—trends which aligned very well with SiFx desorption promoted by steady-state wafer heating. Gas arrival/surface saturation experiments with varying pressures and pulse rates showed that, in straightforward etching discharges such as Ar/SF6, laser removal per pulse plateaus when the pulse rate is lower than the rate of surface saturation, while in fluorocarbon-rich etch chemistries such as Ar/C4F8/O2 mixtures, a minimum pulse rate must be maintained to overcome the CFx polymer layer being deposited.

Improved retention of phosphorus donors in germanium using a non-amorphizing fluorine co-implantation technique

Co-doping with fluorine is a potentially promising method for defect passivation to increase the donor electrical activation in highly doped n-type germanium. However, regular high dose donor-fluorine co-implants, followed by conventional thermal treatment of the germanium, typically result in a dramatic loss of the fluorine, as a result of the extremely large diffusivity at elevated temperatures, partly mediated by the solid phase epitaxial regrowth. To circumvent this problem, we propose and experimentally demonstrate two non-amorphizing co-implantation methods; one involving consecutive, low dose fluorine implants, intertwined with rapid thermal annealing and the second, involving heating of the target wafer during implantation. Our study confirms that the fluorine solubility in germanium is defect-mediated and we reveal the extent to which both of these strategies can be effective in retaining large fractions of both the implanted fluorine and, critically, phosphorus donors.

(Invited) Pattern and Emissivity Insensitive Dopant Activation and Silicide Contact Formation Annealing in a Hot Wall Rapid Thermal Annealing System

Rapid thermal annealing (RTA) enabled shallow junction formation requires very short time annealing at high temperatures for low thermal budget. RTA is typically done by lamp-based radiant heating. Radiant power from lamp arrays is close-loop controlled to execute the temperature of the Si wafer as programmed. The increase of annealing temperature and the decrease of annealing time are generally required for more aggressive device scaling. However, the use of non-equilibrium radiant heat sources (photon energy from lamp arrays) makes the heating process sensitive to the optical properties of the Si wafers. Local temperature non-uniformity during RTA is considered an important contributor for within-die process variations which cause significant problems for advanced complimentary metal-oxide-semiconductor (CMOS) device manufacturing. RTA-induced variations strongly depend on circuit layout patterns and optical properties of exposed materials on the surface of the Si wafers. This phenomenon is often referred to as “pattern effect” known from the early days of RTA introduction in the semiconductor industry. In efforts to reduce the “pattern effect”, various approaches have been proposed and implemented in device manufacturing. Shielding device patterns from the radiant heat source is a common approach, having limited success. It is done by either placing a dummy wafer on the pattern side of the Si wafer or backside heating. One other common approach is to homogenize the optical properties of the pattern side of Si wafer by either adding an optical absorption layer or dummy patterns. A differential thermal energy control technique is also proposed for pattern effect suppression. Non-radiative heating techniques have been proposed and demonstrated effectiveness of this “pattern effect” suppression. In this paper, various silicide contact formations on implanted single crystalline Si in source/drain region and implanted poly-Si in gate region were studied over wide ranges of RTA temperature and time using a hot wall RTA system which uses mainly natural convection and conduction through ambient gas. Dopant profiles of the silicide and doped Si after silicidation in the hot wall RTA system were characterized. Proposed possible silicide formation and dopant diffusion mechanisms are discussed. Differences between radiant heating and non-radiant heating on the silicide formation and dopant profiles are compared. The pattern and emissivity insensitive dopant activation and silicide contact formation annealing results will be introduced and potential applications of the hot wall RTA technique in advanced CMOS devices will be proposed.

Silica nanowire–Au nanoparticle pea-podded composites: Synthesis and structural analyses

Nanoscale wires of silicon oxide, among which some with embedded gold nanoparticles, are synthesized by a standard procedure involving the heating of a gold-coated silicon wafer at temperature higher than 1273K. We report quantitative and systematic structural analyses of the silicon oxide nanowires with embedded gold nanoparticles performed by scanning electron microscopy, transmission electron microscopy, energy filtered transmission electron microscopy, X-ray diffraction, and optical transmittance measurements. For such pea-podded structures, the analyses allow us to correlate the diameter of the nanoparticles with the diameter of the nanowire in which they are embedded, and the diameter of the nanoparticles with their spacing. The results help in understanding the mechanism inducing the formation of such structures and indicate the coexistence of transport and instability processes during the growth stage.

Process Optimization of CoSi2 Formation on P-Doped Poly-Si by Hot Wall-Based Rapid Thermal Annealing

Low resistivity junctions and low resistivity contacts are essential for fabricating high performance devices with advanced device modes. Significant effort has been expended to develop low resistivity junctions, industry wide. However, low resistivity contact formation has not received significant attention, other than changing the silicide of choice, depending on required minimum line width or device node. Once the candidate silicide material is chosen for the device node, relatively small improvement in resistivity has been made in recent years, despite silicidation process optimization which include modifications of process steps and integration schemes. In this study, we have investigated the effect of annealing temperature and time on the resulting resistivity of Co2Si contacts with P-doped poly-Si using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. The hot wall RTA resulted in significantly (>20%) lower Rs, down to 19.6 ohm/sq. from equivalent RTA process using conventional tungsten halogen lamp-based (cold wall) RTA systems over a very wide process window (RTA temperature and time). Secondary ion mass spectroscopy (SIMS) dopant (P) depth profiling results revealed that the P atoms in the CoSi2 film and at the CoSi2/P-doped poly-Si interface, redistribute very differently under different RTA conditions. The same Rs value can be realized by different P profiles resulting from different RTA conditions. To enable contact resistance reduction, P pile-up near the CoSi2/P-doped poly-Si interface for and to suppress P depletion from P-doped poly-Si layer for resistivity reduction, lower temperature RTA for longer times in the hot wall RTA system was found to be beneficial. Wafers with almost identical P depth profiles after CoSi2 formation RTA in the cold wall RTA and the hot wall RTA systems, still showed an Rs difference of ~20%. The wafers annealed in the hot wall RTA system always showed lower Rs values indicating higher P dopant activation in the P-doped poly-Si layer. The difference in wafer heating mechanisms between the cold wall (lamp-based) RTA and the hot wall (furnace-based) RTA may have played an important role in the dopant activation and Rs differences. Hot wall RTA is very promising for realizing the low resistivity contacts required in advanced high performance devices. The simple change of annealing technique may extend the life cycle of CoSi2/P-doped poly-Si contacts. The Rs response surface (as a function of RTA temperature and time) and SIMS depth profiles of P atoms will be presented at the meeting. Figure 1

Influence of the Window Thermal Diffusivity on the Silicon Wafer Temperature in a Rapid Thermal System

The heating of a silicon wafer in a rapid thermal process is studied by numerical simulation. In the model, the equations of conservation of mass and energy are solved with the finite-volume method and the determination of the solutions of the radiative transfer equation is based on the Monte-Carlo method. The results of numerical simulations, without optimization and in steady state, show a close relationship between the thermal profiles of the silicon wafer and the ones of the quartz window. By introducing a high thermal diffusivity value for the window, the homogeneity of the wafer temperature is improved by 54%. The effect of heat storage by the quartz window on the temperature profile of the silicon substrate is hence well appreciated. Finally, a selection of materials is proposed for the implementation of the high diffusivity infrared window.

Deconvoluting the Mechanism of Microwave Annealing of Block Copolymer Thin Films

The self-assembly of block copolymer (BCP) thin films is a versatile method for producing periodic nanoscale patterns with a variety of shapes. The key to attaining a desired pattern or structure is the annealing step undertaken to facilitate the reorganization of nanoscale phase-segregated domains of the BCP on a surface. Annealing BCPs on silicon substrates using a microwave oven has been shown to be very fast (seconds to minutes), both with and without contributions from solvent vapor. The mechanism of the microwave annealing process remains, however, unclear. This work endeavors to uncover the key steps that take place during microwave annealing, which enable the self-assembly process to proceed. Through the use of in situ temperature monitoring with a fiber optic temperature probe in direct contact with the sample, we have demonstrated that the silicon substrate on which the BCP film is cast is the dominant source of heating if the doping of the silicon wafer is sufficiently low. Surface temperatures as high as 240 °C are reached in under 1 min for lightly doped, high resistivity silicon wafers (n- or p-type). The influence of doping, sample size, and BCP composition was analyzed to rule out other possible mechanisms. In situ temperature monitoring of various polymer samples (PS, P2VP, PMMA, and the BCPs used here) showed that the polymers do not heat to any significant extent on their own with microwave irradiation of this frequency (2.45 GHz) and power (∼600 W). It was demonstrated that BCP annealing can be effectively carried out in 60 s on non-microwave-responsive substrates, such as highly doped silicon, indium tin oxide (ITO)-coated glass, glass, and Kapton, by placing a piece of high resistivity silicon wafer in contact with the sample-in this configuration, the silicon wafer is termed the heating element. Annealing and self-assembly of polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP) and polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) BCPs into horizontal cylinder structures were shown to take place in under 1 min, using a silicon wafer heating element, in a household microwave oven. Defect densities were calculated and were shown to decrease with higher maximum obtained temperatures. Conflicting results in the literature regarding BCP annealing with microwave are explained in light of the results obtained in this study.

Synthesis of photocatalytic TiO2 nano-coatings by supersonic cluster beam deposition

In this paper we report on the photocatalytic behavior in gas phase propane oxidation of well-defined TiO2 nanoparticle (NP) coatings prepared via Supersonic Cluster Beam Deposition (SCBD) on Si-wafers and quartz substrates. The temperature dependent crystal phase of the coatings was analyzed by Raman spectroscopy, and the morphology by High Resolution-Scanning Electron Microscopy.SCBD deposition in the presence of oxygen enables the in situ synthesis of TiO2 layers of amorphous NP at room temperature. Adapting the deposition temperature to 500°C or 650°C leads to Anatase crystals of variable size ranges, and layers showing significant porosity. At 800°C mainly Rutile is formed. Post annealing by wafer heating of the amorphous NP prepared at room temperature results in comparable temperature dependent phases and morphologies.Photocatalytic activity in propane oxidation was dependent on the morphology of the samples: the activity decreases as a function of increasing particle size. The presence of water vapor in the propane feed generally increased the activity of the wafer-heated samples, suggesting OH groups are not profoundly present on SCBD synthesized layers. In addition, a remarkable effect of the substrate (Si or Quartz) was observed: strong interaction between Si and TiO2 is largely detrimental for photocatalytic activity.The consequences of these findings for the application of SCBD to synthesize samples for fundamental (spectroscopic) study of photocatalysis are discussed.

Characterization of the Descum Process for Various Silicon Substrates Doping

The descum process is temperature-sensitive process. It has been demonstrated that the process is very sensitive to silicon substrate doping, which impacts wafer heating. A higher doping level caused much higher resist removal when the descum process was ran in a reactor that also ran dry strip processes. The higher level of resist removal was the result of higher wafer surface temperature. The likely causes for higher wafer surface temperature are lower thermal conductivity and higher emissivity of the highly doped wafer substrate.

Multiphysics simulation of a novel concept of MEMS-based solid propellant thruster for space propulsion

This work analyzes a novel MEMS-based architecture of submillimeter size thruster for the propulsion of small spacecrafts, addressing its preliminary characterization of performance. The architecture of microthruster comprises a setup of miniaturized channels surrounding the solid-propellant reservoir filled up with a high-energetic polymer. These channels guide the hot gases from the combustion region towards the nozzle entrance located at the opposite side of the thruster. Numerical simulations of the transient response of the combustion gases and wafer heating in thruster firings have been conducted with FLUENT under a multiphysics modelling that fully couples the gas and solid parts involved. The approach includes the gas-wafer and gas-polymer thermal exchange, burnback of the polymer with a simplified non-reacting gas pyrolysis model at its front, and a slip-model inside the nozzle portion to incorporate the effect of gas-surface and rarefaction onto the gas expansion. Besides, accurate characterization of thruster operation requires the inclusion of the receding front of the polymer and heat transfer in the moving gas-solid interfaces. The study stresses the improvement attained in thermal management by the inclusion of lateral micro-channels in the device. In particular, the temperature maps reveal the significant dependence of the thermal loss on the instantaneous surface of the reservoir wall exposed to the heat flux of hot gases. Specifically, the simulations stress the benefit of implementing such a pattern of micro-channels connecting the exit of the combustion reservoir with the nozzle. The results prove that hot gases flowing along the micro-channels exert a sealing action upon the heat flux at the reservoir wall and partly mitigate the overall thermal loss at the inner-wall vicinity during the burnback. The analysis shows that propellant decomposition rate is accelerated due to surface preheating and it suggests that a delay of the flame extinction into the reservoir is possible. The simulated operation of the thruster concept shows encouraging performance.

Thermal design of hot plate for 300-mm wafer heating in post-exposure bake

Temperature uniformity of a wafer during post-exposure bake (PEB) in lithography is an important factor in controlling critical dimension (CD) uniformity. In this study, a new hot plate system for the PEB of a 300-mm wafer was analyzed and designed. First, temperature deviation on the wafer caused by warpage was investigated, and the heater pattern of the multi-zone hot plate in the bake system was numerically analyzed. Then, a new heater pattern to enhance the temperature uniformity was proposed and tested experimentally. As a result, temperature uniformity within 0.087 °C on a 300-mm wafer was achieved.