Wafer Heating Research Articles

Recent developments in rapid thermal processing

Rapid thermal annealing (RTA) with a short dwell time at maximum temperature is used with ion implantation to form shallow junctions and polycrystalline-Si gate electrodes in complementary, metal-oxide semiconductor (CMOS) Si processing. Wafers are heated by electric lamps or steady heat sources with rapid wafer transfer. Advanced methods use "spike anneals," wherein high-temperature ramp rates are used for both heating and cooling while also minimizing the dwell time at peak temperature to nominally zero. The fast thermal cycles are required to reduce the undesirable effects of transient-enhanced diffusion (TED) and thermal deactivation of the dopants. Because junction profiles are sensitive to annealing temperature, the challenge in spike annealing is to maintain temperature uniformity across the wafer and repeatability from wafer to wafer. Multiple lamp systems use arrayed temperature sensors for individual control zones. Other methods rely on process chambers that are designed for uniform wafer heating. Generally, sophisticated techniques for accurate temperature measurement and control by emissivity-compensated infrared pyrometry are required because processed Si wafers exhibit appreciable variation in emissivity.

Analytical-based solutions for SCALPEL wafer heating

When operating in high-throughput conditions, SCALPELs 100 keV electron beam causes significant dynamic wafer deformation. To complement extensive finite element analysis, we have undertaken an analytical solution to the governing heat transfer and elastic strain equations and boundary conditions. This efficient, Green’s function-based computational approach is able to support a robust and versatile image-placement correction strategy.

STUDIES OF $4{\rm H}\mbox{--}{\rm SiC}(0001){\rm Si}(\sqrt3\times\sqrt3)$ AND (0001)C(3×3) SURFACES AND THEIR METALLIZATION PROCESS BY NI USING STM, AES AND LEED

Several methods have been tried to prepare clean surfaces of 4H–SiC(0001)Si and C, whose surface atomic, or electronic, structures have been studied by LEED (low energy electron diffraction) STM (scanning tunneling microscopy) and AES (Auger electron spectroscopy). Some sequential chemical treatments, for example, agitation in an organic solvent and dipping in HF solution, followed by the heating of a SiC wafer in UHV (ultrahigh vacuum, below 10-7 Pa) at 950°C, gave either a [Formula: see text] or 3×3 superstructure, observed by LEED (low energy electron diffraction), for the SiC(0001) Si or C surface, respectively. An elongated NH4F treatment followed by a heat treatment in UHV at ~950°C gave a rather flat region to be investigated by STM, where a [Formula: see text] superstructure for the SiC(0001) Si surface has been observed. In the case of metal (Ni) atom deposition on SiC(0001) [Formula: see text] and (0001)C(3×3) surfaces, AES and LEED analysis have clarified that deposited metal atoms form islands up to ~5 Å. However, Ni atoms dispersed uniformly at the very beginning of the deposition, which means that the Ni overlayer piles up in layer followed by island growth mode.

Evaluating the effects of thin film patterns on the temperature distribution of silicon wafers during radiant processing

A numerical model was developed to find the temperature distributions during radiant heating of a silicon wafer with SiO2 thin film patterns. The radiative properties of silicon and the film structure were found by considering the effects of partial transparency and thin film interference. The average total properties over simple patterns with feature sizes of the order of a few micrometers were found, using an average of the properties of each region within the pattern, weighted by their relative areas. In general, wafers with a single SiO2 film or pattern reach a higher steady state temperature than a plain Si wafer due to higher total absorptivity. This applies to thin films of any thickness below several micrometers, where coherent effects are dominant. The temperature of patterned wafers vary nonlinearly with film thickness, with the highest temperature discrepancy from Si wafer occurring at film thickness of ~0.2 ?m. For wafers with complex patterns, the temperature distributions can be estimated by the average of temperatures for simpler patterns, weighted by their respective areas. Due to limitations in the computational domain, the radiative processing of 3-in. wafers was modeled; however, results were confirmed for the 12-in. wafer for limited cases.

Monte Carlo study of high performance resists for SCALPEL nanolithography

The semiconductor community continues to push the limits of device dimensions by exploring new high-resolution lithography technology. As part of the SCALPEL lithography resist program, our goal is to be able to print sub-100 nm structures at doses that will permit high throughput, reduce wafer heating and still maintain good process latitude. Using 100 KV exposures on a SCALPEL tool, 100 nm structures were printed at exposure dose of 5.8 μC/cm 2 (and 80 nm isolated trenches at 5.4 μC/cm 2) in positive resists. In negative resists, isolated 100 nm were printed at a dose of 6.8 μC/cm 2, and 80 nm structures at 7.2 μC/cm 2 were resolved as well. These results are well below the 10 μC/cm 2 minimum dose requirement for high throughput. Monte Carlo simulations were used as means to understand energy absorption mechanisms of these e-beam optimized resists, DUV and 193 nm resists. Atomic composition was found to factor in improved resist ionization. The resin (or low-Z elements) is found to account for more than 99% of ionization events during exposure.

Finite element analysis of SCALPEL wafer heating

A high-throughput scattering with angular limitation projection electron beam lithography (SCALPEL) tool will typically deliver up to 1.5×10−4 J to an area of 250 μm×250 μm over a time of 200 μs, corresponding to a power input of 0.75 W. This heat deposition occurs in the upper 60 μm of a wafer creating local thermal strain at the time of image formation, and depends on mask and tool conditions and specific boundary conditions. Initial modeling results indicate expansion-induced peak pattern placement errors of ∼1 nm on a local scale (i.e., a 3 mm effective field size), several nanometers in a chip area, and a few microns overall. Since the use of a mainly predictive correction algorithm is anticipated, it is vital to conduct a rigorous investigation of the heat transfer and strain formation. Results are presented of such an analysis, illustrating the heating response for the fundamental building blocks of the SCALPEL writing strategy.

Initial wafer heating analysis for a SCALPEL lithography system

A high-throughput SCALPEL tool will employ a typical exposure current of 30 μA and electron column potential of 100 KV, delivering power up to ∼3 W through a 0.25 mm (wafer scale) square optical sub-field. Electrons lose energy to form heat in the upper 60 μm of a wafer in vacuum during a sub-field exposure period of ∼200 microseconds, creating significant local wafer heating at the time of image formation. Our initial analysis indicates that expansion-induced pattern placement errors will require a sub-field position correction strategy.

Modeling of 6H-SiC Wafer Heating during RTP by Incoherent Radiation

Modeling of 6H-SiC Wafer Heating during RTP by Incoherent Radiation

Thermoelastic Analysis of Slip Defect Generation on GaAs Wafers

In this work we develop the thermoelastic analysis for prediction of slip defect generation on (001) GaAs wafers, by means of the finite element method taking into account the anisotropic structure and slip system of dislocation. The analysis for a completely circular wafer predicts that longer slip defect lines are generated at the wafer edge of θ=π/8+Δ+nπ/2, 3π/8-Δ+nπ/2 (Δ is about 3°) and the prediction well agrees with the result of the wafer heating experiment. This demonstrates that our anisotropic analysis is more accurate than simple isotropic analysis which predicts slip defect generation at the wafer edge of θ=π/8+nπ/4. According to this thermoelastic analysis, we can additionally confirm that longer slip defect lines are more prone to be generated at the <110> orientation flat (OF) edge than at the circular edge. Finally, we suggest the method of preventing slip defect generation.

Polysilicon RTCVD process optimization for environmentally-conscious manufacturing

In the semiconductor manufacturing industry, optimization of advanced equipment and process designs must include both manufacturing metrics (such as cycle time, consumables cost, and product quality) and environmental consequences (such as reactant utilization and by-product emission). We have investigated the optimization of rapid thermal chemical vapor deposition (RTCVD) of polysilicon from SiH/sub 4/ as a function of process parameters using a physically-based dynamic simulation approach. The simulator captures essential time-dependent behaviors of gas flow, heat transfer, reaction chemistry, and sensor and control systems, and is validated by our experimental data. Significant improvements in SiH/sub 4/ utilization (up to 7/spl times/) and process cycle time (up to 3/spl times/) can be achieved by changes in 1) timing for initiating wafer heating relative to starting process gas flow; 2) process temperature (650-750/spl deg/C); and 3) gas flow rate (100-1000 seem). Enhanced gas utilization efficiency and reduced process cycle time provide benefits for both environmental considerations and manufacturing productivity (throughput). Dynamic simulation proves to be a versatile and powerful technique for identifying optimal process parameters and for assessing tradeoffs between various manufacturing and environmental metrics.

Modeling of Heat Transport and Wafer Heating Effects during Plasma Etching

Uniformity of plasma etching and deposition processes critically depends on the wafer temperature and its spatial variation across the wafer. The goal of this work is to use mathematical modeling to investigate the key factors that determine the wafer temperature and its radial uniformity during plasma etching. Toward this end, a mathematical model of energy transport in and out of a Si wafer in a plasma etching reactor that employs a substrate platen with a He back side cooling arrangement was developed. The possibility of wafer bowing due to high He back side pressure was considered and the effects of ion bombardment flux uniformity, He back side pressure, and different wafer clamping arrangements were studied. While an increase in He back side pressure increases the rate of heat transfer from the wafer to the electrode, excessive He pressure causes the wafer to bow. Bowing increases the electrode‐wafer gap, decreases the heat transfer rate, and adversely affects the temperature uniformity. These effects are most pronounced for large diameter wafers (>200 mm) and are predicted to be very important in the processing of 300 and 400 mm substrates. The manner in which the wafer is clamped to the cooled electrode is another key factor that determines the heat transport at the wafer edge and the radial temperature profile across the wafer. The uniformity of the wafer temperature depends on the heat transport at the wafer edges. Poor thermal contact at the wafer edge leads to a high but uniform wafer temperature; on the other hand, if a good thermal contact is made at the wafer edge, the average temperature is lower but less uniform. Model predictions compared well with the available experimental data.

Monte Carlo Thermal Model of an Integrating Light Pipe for Rapid Thermal Processing

AbstractA Monte Carlo model is developed to simulate transient wafer heating as a function of system parameters in a kaleidoscope- or integrating light-pipe type cavity with square cross-section. Trends in wafer temperature uniformity are examined as a function of length-to-width ratio, cavity width, and the number of heating lamps. The effect on temperature determination by a radiometer placed in the bottom end wall of the cavity is simulated.

A Universal Thermal Module™ for Clusterable RTP and MOCVD Applications

AbstractA Universal Thermal Module™ (UTM™) has been developed for vacuum-integrated cluster RTP and MOCVD as well as stand-alone atmospheric RTP applications. The UTM™ architecture provides highly modular RTP and MOCVD tool configurations for various single-wafer thermal processes. The UTM™ design comprises a temperature-controlled UHV-grade process chamber as well as an ultraclean gearless wafer rotation assembly for improved temperature uniformity and enhanced built-in reliability. The UTM™ RTP employs bottom/backside wafer heating using a multi-zone axisymmetric illuminator and a reflective multi-zone gas showerhead located above the wafer. Precision RTP control is achieved using a multi-zone controller in conjunction with a multipoint sensor system with real-time multi-zone compensations for wafer emissivity and illuminator light interference effects. The RTP temperature measurement and control techniques fully compensate for any axisymmetric or non-axisymmetric wafer emissivity patterns, eliminating the need for pre-RTP wafer backside conditioning. The UTM™ showerhead provides capabilities for ultraclean multi-zone gas injection and in-situ RF plasma for MOCVD and RTCVD processes. The UTM™ MOCVD module meets the most stringent specifications and tool parameters for various metallization and high-K dielectric deposition applications. This module has been used for deposition of low-resistivity copper films with excellent void-free sub-half-micron gap fill for high-performance multilevel interconnects. The UTM™ RTP and MOCVD modules have been implemented based on design optimizations in a virtual reactor environment.

Modeling an inductively coupled plasma source

Inductively coupled plasma (ICP) sources are becoming increasingly popular for etching submicrometer features, soft-cleans for physical vapor deposition cluster tools, and plasma-enhanced chemical-vapor deposition. Here, we report on a discharge model for argon for the ICP which combines an electromagnetic field distribution model with an ambipolar diffusion model. The model provides a self-consistent solution for the spatial distribution of the charged species in the bulk plasma, which permits the spatial distribution of the ion flux to the wafer surface to be calculated. The variations of the peak electron concentration, the ion flux, and its uniformity at the wafer have been simulated as a function of the rf power, antenna geometry, and chamber geometry. The electron number density increases linearly with rf power in accordance with experimental observations. The ion flux uniformity is primarily dependent on the diameter of the antenna and is only slightly dependent on the number of turns. The uniformity generally is relatively invariant with rf power above a threshold power level. Contouring the antenna or the dielectric separating the antenna from the plasma is useful for improving ion flux uniformity. The minimum thickness of the dielectric cap is constrained by the maximum allowable sheath potential. The induced electric field at the wafer can cause substantial wafer heating at high antenna power levels. Increasing the wafer to antenna spacing mitigates this problem without sacrificing the ion flux and its uniformity.

Electron cyclotron resonance plasma reactor for cryogenic etching

Electron cyclotron resonance (ECR) plasma reactors are being used for ultralarge scale integrated circuit fabrication to meet the stringent requirements on submicron feature etching. Three issues are critical for ECR reactor design: plasma uniformity, ion energy control, and wafer temperature control. Plasma uniformity is important for minimizing over etch times and reducing the probability of producing charging damage. Ion energy control is needed to optimize etching rate, anisotropy, and selectivity without compromising device yield. Wafer temperature control is important because large ion currents at low pressure can result in wafer heating and thereby alter the rates of surface chemical processes. An ECR plasma reactor is described that is designed to etch compound semiconductors and Si at low temperatures (−170 to 20 °C), where superior selectivity and linewidth control are achievable. By measuring dc bias, floating potential, and ion saturation current densities it is shown that ion energies in this system can be controlled by applying an rf bias to the sample. To characterize plasma uniformity, the radial ion density profile is measured using a fast injection Langmuir probe. Hollow, peaked, or uniform radial plasma density profiles can be obtained depending on microwave power, pressure, and magnetic field. Plasma density profiles are influenced by microwave absorption and refraction which, in turn, are influenced by both the magnetic field and plasma density profiles. The net result is a strong coupling between wave propagation and charge particle transport. To control wafer temperature a cryogenic electrode capable of maintaining a wafer temperature to ±2.5 °C at −170 °C is used while the wafer is exposed to an electron cyclotron resonance plasma. The sample temperature is monitored using infrared laser interferometric thermometry and the heat flux to the wafer surface in an Ar plasma is measured as a function of operating parameters by monitoring temperature transients as the discharge is gated on and off.

Semiconductor processing with plasma implantation

An updated survey of plasma immersion ion implantation (PIII) applications in semiconductor processing is presented. PIII is a technique in which a negative bias extracts ions directly from a plasma to be implanted into a substrate immersed in the plasma. This technique offers the advantage of high dose-rate implantation at low energies and large area processing capability over conventional implanters with more compex design. PIII has been applied to semiconductor processing in the formation of shallow junctions, poly doping, impurity gettering, Pd seeding for Cu interconnects and conformal doping of trenches. While PIII has inherent advantages, such as built-in wafer charge neutralization, issues such as contamination, wafer heating, secondary electron generation, and substrate interactions with the plasma remain concerns.

Modeling of Plasma Etching Reactors Including Wafer Heating Effects

A comprehensive mathematical model of chlorine etching of polysilicon in a single‐wafer plasma reactor was developed from first principles. Wafer heat transport was included as an integral part of the analysis. The model provided the spatiotemporal variations of etchant concentration, wafer temperature, and etch rate. Under conditions of high etch rate and poor wafer cooling, etching was inherently transient. The polysilicon etch rate increased with time despite the fact that the atomic chlorine concentration decreased with time. This was due to wafer heating and the Arrhenius dependence of etch rate on temperature. Multichannel laser interferometry was developed to monitor the spatiotemporal variations of etch rate in real time. Measured etch rate transients compared favorably with model predictions. Results were sensitive to surface reaction parameters and to wafer back side cooling.

Heat transfer in a microelectronics plasma reactor

Plasma etching has became an indispensible technique for microelectronics device manufacturing. However, its application is often limited by the wafer temperature increase due to the ion bombardment, which may exceed the susceptor temperature by as much as 200 °C when the semiconductor wafer is loosely lying on the cooled susceptor. The aim of this study is to perform an accurate evaluation of heat transfer in an industrial etching reactor, and in particular to point out the critical role of the susceptor/substrate interface in this problem of damageable overheating. The required experimental precision, necessary to reach this goal, is based on in situ temperature monitoring via fluoroptometry, and on electrical characterization of the plasma to investigate the effective heating power dissipated on the substrate. It is thus shown that the only wafer heating source to be considered is the real electrical rf power dissipated in the plasma, and that the heated substrate evacuates the main part of this power to the cooled susceptor, via thermal conduction through the residual gas present in the interface between these two elements. A non-negligible part of energy can also be lost via thermal radiation. The thermal conduction through the interface is shown to be strongly dependent on the gas pressure, and the quasilinear rate obtained is evidence for the molecular regime of the gas molecules in this region. The type of gas also strongly affects the interface heat flow, and in a quite uncommon way: an effect of thermal conductance inversion between two different types of gases when the pressure decreases is observed. A criterion is proposed to evaluate a priori and in a qualitative point of view whether a given couple of gases may exhibit this effect, which consequences are very important from a technological point of view.

Rapid Thermal Processor Modeling, Control, and Design for Temperature Uniformity

ABSTRACTWith the ability to perform heat cycles on a wafer quickly and within low thermal budgets, Rapid Thermal Processor (RTP) systems offer potential advantages over conventional furnaces. However, RTP' have an inherent problem with wafer temperature uniformity which can cause process nonuniformity and wafer stress.In this work, a thermodynamic model of a wafer is used to form an understanding of the wafer heating problem. This model shows that an idealized heating flux density profile can maintain thermal uniformity at steady-state temperatures. This profile uniformly heats the wafer while counteracting the additional cooling at the wafer edge. However, this profile induces temperature nonuniformities during wafer temperature transients, such as overheating of the edge during temperature rises. Therefore, a dynamic flux-density profile is needed during temperature transients to ensure continuous temperature uniformity. The model is used to predict the steady-state and dynamic profiles required to process a wafer with complete temperature uniformity. The predicted profiles can be used to adapt an RTP chamber and control system to approach production of uniform wafers and also for the design of new systems. This paper will explain the theory of wafer heating, describe the dynamic profiles required for continuous uniformity, review the wafer model, show the result of an idealized profile for steady state and transients processing, and present a new control methodology to achieve uniform temperatures.

Materials

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