Vth Values Research Articles

Electrical conduction and switching properties of As2O3·V2O5·FeO glasses

Electrical conductivity, negative resistance and joule heating characteristics for x%As2O3·(80-x)%V2O5·20%FeO bulk glasses with (25 ≤ x ≤ 45), have been investigated at various temperatures, frequencies and thicknesses. Electrical conductivity is found to increase from 3 × 10−5 to 0.012 Ω−1 m−1 depending on the composition. The experimental results for electrical conductivity has been analyzed using varies models. The dc activation energy (Edc) is estimated to be in the range 0.25–0.5 eV depending on the value of x. According to the multi phonon hopping model, the dc conductivity is found to be relative to Tp with the exponent p between 8.2 and 10.5. The fitted data of the ac conductivity according to Dyre’s percolation path approximation and Almond–West power law equation showed an excellent collapse to a single master curve. This indicates that there is a good time–temperature superposition in these glasses. Threshold switching type is detected in all the samples with maximum current of about 3 mA. The threshold voltage Vth values are affected by ambient temperature, sample thickness and sample composition ratios. The activation energy for switching is found to decrease with increasing the percentage of As2O3. Variations of the surface temperature during the switching cycles suggest the applicability of the electrothermal mechanism.

Complementary p-Channel and n-Channel SiC MOSFETs for CMOS Integration

The fabrication of CMOS devices in SiC is important for both a higher operating temperature capability and the integration with SiC power devices. In this work, n-channel and p-channel signal MOSFETs have been successfully fabricated using a process technology fully compatible with our HV SiC VDMOS technology. A preliminary SiC CMOS inverter has been also integrated. The gate oxide configuration includes the use of Boron to improve SiO2/SiC. Electrical characterizations have been carried out at room temperature and a summary of the results is presented. The biggest challenge is to balance the n-type and p-type MOSFETs not only in area but also in Vth value.

Impact of X-Ray Radiation on SOI Mosfet: Insulator Film Degradation and Hot-Carrier Reliability

This paper discusses the impact of X-ray radiation in the SOI MOSFET in terms of hot-carrier reliability. We examine sub-micron complimentary SOI MOSFETs in order to investigate the various factors influencing device characteristics [1]. All devices were fabricated using conventional photolithography in the 1990s, and after fabrication were subjected to continuous X-ray radiation in the range of 1J/cm2 to 10J/cm2. N-channel MOSFETs are inversion-channel devices, and p-channel MOSFETs are buried-channel devices. They have 0.36-μm or 1-μm channel length and 4.5-μm or 20.6-μm channel width. Some devices were annealed at 400 C with the ambient being the forming gas. D. C. characteristics of as-irradiated devices and post-annealed devices and hot-carrier reliability of post-annealed devices were fully investigated. Figure 1 shows front ID-VG transfer characteristics of X-ray irradiated nMOS devices and post-annealed nMOS devices. It is seen that X-ray irradiation increases the gate SiO2/SOI interface state density (Dit) and that annealing under the forming gas reduced the Dit value to almost the same value as the non-irradiated device. Figure 2 shows back ID-VB transfer characteristics of X-ray irradiated nMOS devices and post-annealed nMOS devices, where VB is the substrate voltage. It is seen that positive ionized charges are generated inside the buried oxide with 10-J/cm2 X-ray radiation, and that SOI/buried oxide interface state density increased with 1-J/cm2 and 5-J/cm2 X-ray radiation. The Dit values are not reduced to those of non-irradiated devices and non-negligible band-to-band tunneling current around the drain junction is present. It is anticipated that electron trap sites are generated inside the buried oxide but near the SOI/buried oxide [2]. Figure 3 shows front ID-VG transfer characteristics of X-ray irradiated pMOS devices and post-annealed pMOS devices. It is seen that X-ray irradiation alters the threshold voltage (VTH); the annealing under the forming gas reduced the VTH value to almost the same value as the non-irradiated device. In addition, it is seen that X-ray irradiation increases the SOI/buried oxide interface states density (Dit); the annealing under the forming gas reduced the Dit value to almost reduced the same value as the non-irradiated device. This suggests that holes near the SOI/buried oxide are not sensitive to the behavior of trap sites generated inside the buried oxide. Figure 4 shows back ID-VB transfer characteristics of X-ray irradiated pMOS devices and post-annealed pMOS devices. It is seen that the positive ionized charges are generated inside the gate SiO2, regardless of integrated X-ray radiation energy, and that the gate SiO2/SOI interface state density increases regardless of the integrated X-ray radiation energy. The Dit values and VTH values are recovered by annealing in the forming gas. The above experimental results are summarized as X-ray radiation generates gate SiO2/SOI interface states around the midgap of Si.X-ray radiation generates positive ionized traps inside the buried oxide and the SOI/buried oxide interface states.Electron trap sites are generated inside the buried oxide but near the SOI/buried oxide; these sites are not readily eliminated by annealing in the forming gas.Holes are not sensitive to the behavior of trap sited generated inside the buried oxide. Finally, we investigated the hot-carrier immunity of X-ray irradiated 0.36-μm gate devices. The results of pMOS devices suggest that their lifetime is strongly influenced by the SOI/buried oxide interface property, while the lifetime behavior of nMOS devices is insensitive to the SOI/buried oxide interface property. In summary, our analysis of device characteristics strongly suggests that SOI MOSFETs have high immunity to X-ray irradiation. The devices examined here worked over 20 years after their fabrication. It can be considered that chemical structures of the thermal SiO2 film and the buried oxide film played important roles in achieving such robustness [3-5].

Reliability Studies on AlGaN/GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors with Through-Substrate via Technique and Backside Heat Sink Metal on Silicon-on-Insulator Substrates

AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) on silicon-on-insulator (SOI) substrates using the through-substrate via (TSV) and back side metal techniques are studies for improving thermal dissipation and device performances. The measured VTH values of the standard (SOI w/o TSV) and MIS-HEMT with TSV (SOI-TSV) devices are −4.1 and −3.9 V. The drain ON/OFF current ratio (ION/IOFF) values of SOI w/o TSV and SOI-TSV devices are 12.96 and 61.62 and the subthreshold swing of these two structures are 248 and 226 mV/dec. The results show that the reduced vertical leakage current in SOI-TSV device exhibited better ION/IOFF ratio and the subthreshold swing than the SOI w/o TSV device. In gate-to-drain current-voltage characteristics, the SOI-TSV devices shows a lower leakage current under the VGS from 0 to −10 V operation than the standard device. Additionally, the reliability and the trapping phenomenon of these two devices were studied using low-frequency noise and pulse measurements. Based on these two structures were processed on the same wafer, the better heat dissipation of SOI-TSV device with Ti/Al back side layer decreases the generation of hot carriers at the reliability stress measurement.

Stability Behavior of Self-Aligned Coplanar a-IGZO Thin Film Transistors Fabricated by Deep Ultraviolet Irradiation

We fabricated self-aligned coplanar amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs and defined the source/drain region using deep ultraviolet (DUV) irradiation. For our TFTs, source/drain region were well defined to designed dimensions and contact resistance was low value. The electrical properties of the device show field-effect mobility (μFE) of 13.2 cm2/Vs, subthreshold swing (S/S) of 0.32 V/decade, threshold voltage (Vth) of 3.2 V, and on/off ratio of 8.8 × 108, respectively. In addition, the reduced channel length (ΔL) and width-normalized contact resistance (RSDW) were 1.08 μm and 87.5 Ω cm, respectively. Stability behavior of self-aligned coplanar a-IGZO TFT fabricated by DUV irradiation was investigated under negative bias stress (NBS), negative bias illumination stress (NBIS), positive bias stress (PBS), and positive bias temperature stress (PBTS). After the stress under NBS, NBIS, PBS, and PBTS, the Δ Vth values of −0.3 V, −0.8 V, 1.2 V, and 1.3 V were measured, respectively. Additionally, the electrical characteristics of the n+ doping region by DUV irradiation were not degraded under any of the stress conditions.

Natural polymers for disposable organic thin film transistors

Abstract In this study, eco-friendly PTCDI-C8–based organic thin film transistors (OTFTs) were fabricated by incorporating polymers from renewable sources as gate dielectrics and substrates. Chitosan, a polysaccharide obtained from the deacetylation of chitin, and natural rubber (NR), extracted from natural rubber tree, have good dielectric properties, biocompatibility, and biodegradability. To examine the practical applicability of these materials, we fabricated OTFTs using bilayer PVPy/NR and chitosan/NR films as gate dielectric materials. NR not only improved the insulation properties of the dielectric film but also acted as a surface modifier. The fabricated OTFT incorporating chitosan/NR dielectric operated under a low driving voltage, with values of μ and Vth of 0.027 cm2V−1s−1 and 0.83 V, respectively. It also displayed an electrical response in the presence of DNA at different concentrations. Because, chitosan possesses high transparency and good mechanical properties, it can be readily cast to form transparent flexible substrates. Accordingly, a flexible disposable OTFT device was fabricated using PVPy/NR as the dielectric material on chitosan as the substrate. The disposable device exhibited a carrier mobility of 0.011 cm2V−1s−1, a value of Vth of 0.83 V, and an on/off ratio of 103, while being workable over 100 bending cycles.

Impact of an Interfacial Layer on the Electrical Performance of p‐Channel Tin Monoxide Field‐Effect Transistors

This study examined the insertion effect of an interfacial, 7‐nm‐thick SiNx and SiOF layer on the performance of p‐channel tin monoxide (SnO) field‐effect transistors (FETs). The control SnO FETs, which had a thermal SiO2 gate dielectric, exhibited a mobility, gate swing, threshold voltage (VTH) and ION/OFF ratio of 2.8 cm2 V−1s−1, 6.9 V decade−1, 19.0 V, and 1.8 × 103, respectively. The SiNx‐inserted SnO FETs showed a loss in drain current modulation due to the creation of interfacial trap states. In contrast, the gate swing and VTH values were improved substantially to 5.4 V decade−1 and 2.0 V for the SiOF‐inserted SnO FETs, respectively, whereas the comparable mobility and ION/OFF ratio were preserved. The rationale of the improvement is discussed with respect to Fermi‐energy pinning based on the valence band spectra.

Influence of different conditions on the electrical performance of amorphous InGaZnO thin-film transistors with HfO2/SiNx stacked dielectrics

The electrical performance of HfO2/SiNx stacked dielectric amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) fabricated using different oxygen flow rates, channel thicknesses, annealing temperatures, and deposition powers was investigated. The results showed that when the thin films were deposited with a higher oxygen flow rate, the device saturation mobility (μsat) decreased while transfer curves shifted positively. Free carriers accumulated easily at the interfaces with higher channel thicknesses, which led to the increase in device mobility. The electrical characteristics of the a-IGZO TFTs were strongly affected by annealing temperature. This was because annealing generated free carriers and oxygen vacancies, which resulted in a negative shift in threshold voltage (Vth) and an increase in μsat. An a-IGZO TFT deposited with suitable parameters showed excellent electrical performance: a Vth value of 3.4 V, a saturation mobility of 18.1 cm2 V−1 s−1, an on/off current ratio of 108, and a subthreshold swing of 137 mV dec−1.

Impact of contact resistance on the electrical properties of MoS2 transistors at practical operating temperatures.

Molybdenum disulphide (MoS2) is currently regarded as a promising material for the next generation of electronic and optoelectronic devices. However, several issues need to be addressed to fully exploit its potential for field effect transistor (FET) applications. In this context, the contact resistance, RC, associated with the Schottky barrier between source/drain metals and MoS2 currently represents one of the main limiting factors for suitable device performance. Furthermore, to gain a deeper understanding of MoS2 FETs under practical operating conditions, it is necessary to investigate the temperature dependence of the main electrical parameters, such as the field effect mobility (μ) and the threshold voltage (Vth). This paper reports a detailed electrical characterization of back-gated multilayer MoS2 transistors with Ni source/drain contacts at temperatures from T = 298 to 373 K, i.e., the expected range for transistor operation in circuits/systems, considering heating effects due to inefficient power dissipation. From the analysis of the transfer characteristics (ID−VG) in the subthreshold regime, the Schottky barrier height (ΦB ≈ 0.18 eV) associated with the Ni/MoS2 contact was evaluated. The resulting contact resistance in the on-state (electron accumulation in the channel) was also determined and it was found to increase with T as RC proportional to T3.1. The contribution of RC to the extraction of μ and Vth was evaluated, showing a more than 10% underestimation of μ when the effect of RC is neglected, whereas the effect on Vth is less significant. The temperature dependence of μ and Vth was also investigated. A decrease of μ proportional to 1/Tα with α = 1.4 ± 0.3 was found, indicating scattering by optical phonons as the main limiting mechanism for mobility above room temperature. The value of Vth showed a large negative shift (about 6 V) increasing the temperature from 298 to 373 K, which was explained in terms of electron trapping at MoS2/SiO2 interface states.

Modeling, Simulation, and Analysis of Novel Threshold Voltage Definition for Nano-MOSFET

Threshold voltage (VTH) is the indispensable vital parameter in MOSFET designing, modeling, and operation. Diverse expounds and extraction methods exist to model the on-off transition characteristics of the device. The governing gauge for efficient threshold voltage definition and extraction method can be itemized as clarity, simplicity, precision, and stability throughout the operating conditions and technology node. The outcomes of extraction methods diverge from the exact values due to various short-channel effects (SCEs) and nonidealities present in the device. A new approach to define and extract the real value of VTH of MOSFET is proposed in the manuscript. The subsequent novel enhanced SCE-independent VTH extraction method named “hybrid extrapolation VTH extraction method” (HEEM) is elaborated, modeled, and compared with few prevalent MOSFET threshold voltage extraction methods for validation of the results. All the results are verified by extensive 2D TCAD simulation and confirmed analytically at various technology nodes.

Control of positive and negative threshold voltage shifts using ultraviolet and ultraviolet-ozone irradiation

The precise control of the threshold voltage (Vth) required to turn a metal-oxide semiconductor field-effect transistor on/off at the designed voltage was important to ensure that the Vth was constant for all the transistors in the circuit. In this study, Vth was adjusted in both the negative and positive directions by manipulating the number of O vacancies on the surface of an oxide nanowire channel using ultraviolet (UV) and UV-ozone (UVO) irradiation. UV irradiation shifted the Vth in the negative direction by an amount that increased with increasing exposure time (−0.96 V at 1 min, −1.42 V at 2 min, and −1.70 V at 3 min), whereas UVO irradiation shifted the Vth in the positive direction by an amount that increased with increasing exposure time (+0.37 V at 3 min, +0.69 V at 5 min, and +1.07 V at 10 min). The shifted values of Vth were maintained by passivating the channel region of the oxide nanowire with an octadecylphosphonic acid self-assembled monolayer.

High-k ZrO2/Al2O3 bilayer on hydrogenated diamond: Band configuration, breakdown field, and electrical properties of field-effect transistors

A band configuration of a high-k ZrO2/Al2O3 bilayer on hydrogenated diamond (H-diamond), a breakdown field (EB) of the ZrO2/Al2O3 bilayer, and an effect of gate-drain distance (dG-D) on electrical properties of ZrO2/Al2O3/H-diamond metal-insulator-semiconductor field-effect transistors (MISFETs) have been investigated. The Al2O3 and ZrO2 layers are successively deposited on H-diamond by atomic layer deposition (ALD) and sputtering-deposition (SD) techniques, respectively. The thin ALD-Al2O3 buffer layer with 4.0 nm thickness plays a role in protecting the H-diamond surface from being damaged by the plasma discharge during SD-ZrO2 deposition. The ZrO2/Al2O3 heterojunction has a type I band structure with valence and conduction band offsets of 0.6 ± 0.2 and 1.0 ± 0.2 eV, respectively. The valence band offset between ZrO2 and H-diamond is deduced to be 2.3 ± 0.2 eV. The EB of the ZrO2/Al2O3 bilayer is measured to be 5.2 MV cm−1, which is larger than that of the single ZrO2 layer due to the existence of the ALD-Al2O3 buffer layer. The dependence of dG-D on drain-source current maximum (IDS,max), on-resistance (RON), threshold voltage (VTH), and extrinsic transconductance maximum (gm,max) of the MISFETs has been investigated. With increasing dG-D from 4 to 18 μm, the absolute IDS,max decreases from 72.7 to 40.1 mA mm−1, and the RON increases linearly from 83.3 ± 5 to 158.7 ± 5 Ω mm. Variation of VTH values of around 1.0 V is observed, and the gm,max is in the range between 8.0 ± 0.1 and 13.1 ± 0.1 mS mm−1.

Impact of Al Doping Concentration at Channel Region on Mobility and Threshold Voltage Instability in 4H-SiC Trench N-MOSFETs

The effect of Al doping concentration (NA) at channel regions ranging from 1.0×1017 to 4.0×1017 cm-3 on the effective channel mobility of electron (μeff) and the threshold voltage (Vth) instability under the positive bias-temperature-stress conditions has been investigated througu the use of trench-gate 4H-SiC MOSFETs with m-face (1-100) channel regions. It was found that μeff degraded with an increase in NA. On the other hand, the increase of NA enlarged the Vth instability. These results indicate that NA has a large impact not only on the Vth value but also on the channel resistance and reliability in 4H-SiC trench MOSFETs.

Limitations of threshold voltage engineering of AlGaN/GaN heterostructures by dielectric interface charge density and manipulation by oxygen plasma surface treatments

The interface charge density between the gate dielectric and an AlGaN/GaN heterostructure has a significant impact on the absolute value and stability of the threshold voltage Vth of metal-insulator-semiconductor (MIS) heterostructure field effect transistor. It is shown that a dry-etching step (as typically necessary for normally off devices engineered by gate-recessing) before the Al2O3 gate dielectric deposition introduces a high positive interface charge density. Its origin is most likely donor-type trap states shifting Vth to large negative values, which is detrimental for normally off devices. We investigate the influence of oxygen plasma annealing techniques of the dry-etched AlGaN/GaN surface by capacitance-voltage measurements and demonstrate that the positive interface charge density can be effectively compensated. Furthermore, only a low Vth hysteresis is observable making this approach suitable for threshold voltage engineering. Analysis of the electrostatics in the investigated MIS structures reveals that the maximum Vth shift to positive voltages achievable is fundamentally limited by the onset of accumulation of holes at the dielectric/barrier interface. In the case of the Al2O3/Al0.26Ga0.74N/GaN material system, this maximum threshold voltage shift is limited to 2.3 V.

Effective work function engineering for a TiN/XO(X = La, Zr, Al)/SiO2 stack structures

In this study, we demonstrated that work function engineering is possible over a wide range (+200 mV to −430 mV) in a TiN/XO (X = La, Zr, or Al)/SiO2 stack structures. From ab initio simulations, we selected the optimal material for the work function engineering. The work function engineering mechanism was described by metal diffusion into the TiN film and silicate formation in the TiN/SiO2 interface. The metal doping and the silicate formation were confirmed by transmission electron microscopy and energy dispersive spectroscopy line profiling, respectively. In addition, the amount of doped metal in the TiN film depended on the thickness of the insertion layer XO. From the work function engineering technique, which can control a variety of threshold voltages (Vth), an improvement in transistors with different Vth values in the TiN/XO/SiO2 stack structures is expected.

Electrical and switching behavior of quaternary defect chalcopyrite CdInGaSe4 thin films

CdInGaSe4 thin films were prepared by thermal evaporation technique. The amorphous nature of the thin films was confirmed by X-ray analysis. The elemental composition of thin film samples was determined by energy-dispersive X-ray spectrometry revealing the stoichiometric compositions of the material. The temperature and thickness dependences of DC electrical conductivity σDC were studied, in the temperature and thickness ranges (303–423 K) and (71–198 nm), respectively. The results indicate that the conduction occurs through a thermally activated process having two conduction levels. The switching phenomenon was studied; the obtained I–V curves are typical for memory switch. The value of Vth increases with film thicknesses, while it decreases exponentially with increasing temperature. The value of threshold field Eth calculated and found to decrease with increasing temperature. The ratio between the threshold activation energy Δɛth and the electrical activation energy ΔEσ2 was calculated and found to be (\(\frac{{\Delta \varepsilon_{\text{th}} }}{{\Delta E_{\sigma 2} }}\) ≈ 0.93 eV), which can be explained according to thermal model. Values of ΔTbreakdown were also calculated and found to increase with temperature.

Organic/inorganic interfaced field-effect transistor properties with a novel organic semiconducting material

A novel 1,3,4-oxadiazole-substituted benzo[b]triphenylene was synthesized by three-step synthetic procedure and OFET device design was successfully designed after theoretical calculations made using Gaussian software. For investigating the field-effect properties of designed organic electronic device, a SiO2 (300 nm) was thermally grown on p-Si wafer at 1000 °C as a dielectric layer and gate, source and drain contacts have been deposited using Au metal with physical vapour deposition. 1,3,4-Oxadiazole-substituted benzo[b]triphenylene was spin coated on the source and drain electrodes of our device, forming organic/inorganic interfaced field-effect transistors. Surface morphology and thin film properties were investigated using AFM. All electrical measurements were done in air ambient. The device showed a typical p-type channel behaviour with increasing negative gate bias voltage values. Our results have surprisingly shown that the saturation regime of this device has high mobility (μFET), excellent on/off ratio (Ion/Ioff), high transconductance (gm) and a small threshold voltage (VTh). The values of μFET, Ion/Ioff, gm and VTh were found as 5.02 cm2/Vs, 0.7 × 103, 5.64 μS/mm and 1.37 V, respectively. These values show that our novel organic material could be a potential candidate for organic electronic device applications in the future.

Comparative Methodical Assessment of Established MOSFET Threshold Voltage Extraction Methods at 10-nm Technology Node

Threshold voltage (VTH) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise VTH value of the device is extracted and evaluated by several estimation techniques. However, these assessed values of VTH diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. Numerous prevalent VTH extraction methods are discussed. All the results are verified by extensive 2-D TCAD simulation and confirmed through analytical results at 10-nm technology node. Aim of this research paper is to explore and present a comparative study of largely applied threshold extraction methods for bulk driven nano-MOSFETs especially at 10-nm technology node along with various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented to infer the most appropriate extraction method at nanometer technology nodes.

Influence of Optimization of Process Parameters on Threshold Voltage for Development of HfO2/TiSi218 nm PMOS

Manufacturing a 18-nm transistor requires a variety of parameters, materials, temperatures, and methods. In this research, HfO 2 was used as the gate dielectric ad TiO 2 was used as the gate material. The transistor HfO 2 /TiSi 2 18-nm PMOS was invented using SILVACO TCAD. Ion implantation was adopted in the fabrication process for the method’s practicality and ability to be used to suppress short channel effects. The study involved ion implantation methods: compensation implantation, halo implantation energy, halo tilt, and source–drain implantation. Taguchi method is the best optimization process for a threshold voltage of HfO 2 /TiSi 2 18-nm PMOS. In this case, the method adopted was Taguchi orthogonal array L9. The process parameters (ion implantations) and noise factors were evaluated by examining the Taguchi’s signal-to-noise ratio (SNR) and nominal-the-best for the threshold voltage (VTH). After optimization, the result showed that the VTH value of the 18-nm PMOS device was -0.291339.

Effects of interface and bulk properties of gate-dielectric on the performance and stability of hydrogenated amorphous silicon thin-film transistors

In order to investigate the effects of interface and bulk properties of gate insulator on the threshold voltage (Vth) and the gate-bias induced instability of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs), four kinds of TFT structures were fabricated with SiNx and SiOx insulators stacked to make different combinations of the bulk and interface in the gate-dielectric layers. It was found that the Vth and the stability are independently controlled by tuning stoichiometry and thickness of the SiOx insertion layer between a-Si:H and SiNx. In TFTs with SiOx insertion layer of 50 nm thickness, on increasing oxygen/silicon (O/Si = x) ratio from 1.7 to 1.9, Vth increased from 0 V to 9 V. In these TFTs with a relatively thick SiOx insertion layer, positive Vth shift with negative bias stress was observed, confirmed to be due to defect creation in a-Si:H with the thermalization barrier energy of 0.83 eV. On reducing the thickness of the SiOx insertion layer down to approximately 1 nm, thin enough for hole injection through SiOx by tunneling effect, stable operation was obtained while keeping the high Vth value under negative stress bias. These results are consistently explained as follows: (1) the high value for Vth is caused by the dipole generated at the interface between a-Si:H and SiOx; and (2) two causes for Vth shift, charge injection to the gate insulator and defect creation in a-Si:H, are mutually related to each other through the “effective bias stress,” Vbseff = Vbs – ΔVfb (Vbs: applied bias stress and ΔVfb: flat band voltage shift due to the charge injection). It was experimentally confirmed that there should be an optimum thickness of SiOx insertion layer of approximately 1 nm with stable high Vth, where enhanced injection increases ΔVfb, reduces Vbseff to reduce defect creation, and totally minimizes Vth shift.