Impact of an Interfacial Layer on the Electrical Performance of p‐Channel Tin Monoxide Field‐Effect Transistors

Abstract

This study examined the insertion effect of an interfacial, 7‐nm‐thick SiNx and SiOF layer on the performance of p‐channel tin monoxide (SnO) field‐effect transistors (FETs). The control SnO FETs, which had a thermal SiO2 gate dielectric, exhibited a mobility, gate swing, threshold voltage (VTH) and ION/OFF ratio of 2.8 cm2 V−1s−1, 6.9 V decade−1, 19.0 V, and 1.8 × 103, respectively. The SiNx‐inserted SnO FETs showed a loss in drain current modulation due to the creation of interfacial trap states. In contrast, the gate swing and VTH values were improved substantially to 5.4 V decade−1 and 2.0 V for the SiOF‐inserted SnO FETs, respectively, whereas the comparable mobility and ION/OFF ratio were preserved. The rationale of the improvement is discussed with respect to Fermi‐energy pinning based on the valence band spectra.