Effects of interface and bulk properties of gate-dielectric on the performance and stability of hydrogenated amorphous silicon thin-film transistors

Abstract

In order to investigate the effects of interface and bulk properties of gate insulator on the threshold voltage (Vth) and the gate-bias induced instability of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs), four kinds of TFT structures were fabricated with SiNx and SiOx insulators stacked to make different combinations of the bulk and interface in the gate-dielectric layers. It was found that the Vth and the stability are independently controlled by tuning stoichiometry and thickness of the SiOx insertion layer between a-Si:H and SiNx. In TFTs with SiOx insertion layer of 50 nm thickness, on increasing oxygen/silicon (O/Si = x) ratio from 1.7 to 1.9, Vth increased from 0 V to 9 V. In these TFTs with a relatively thick SiOx insertion layer, positive Vth shift with negative bias stress was observed, confirmed to be due to defect creation in a-Si:H with the thermalization barrier energy of 0.83 eV. On reducing the thickness of the SiOx insertion layer down to approximately 1 nm, thin enough for hole injection through SiOx by tunneling effect, stable operation was obtained while keeping the high Vth value under negative stress bias. These results are consistently explained as follows: (1) the high value for Vth is caused by the dipole generated at the interface between a-Si:H and SiOx; and (2) two causes for Vth shift, charge injection to the gate insulator and defect creation in a-Si:H, are mutually related to each other through the “effective bias stress,” Vbseff = Vbs – ΔVfb (Vbs: applied bias stress and ΔVfb: flat band voltage shift due to the charge injection). It was experimentally confirmed that there should be an optimum thickness of SiOx insertion layer of approximately 1 nm with stable high Vth, where enhanced injection increases ΔVfb, reduces Vbseff to reduce defect creation, and totally minimizes Vth shift.