Vt Variation Research Articles

Low Power and High Variation Tolerant 9T-SRAM Cell at 16-nm Technology Node

Objectives: The objective of this paper is to design a threshold voltage (Vt) variation tolerant low leakage low power SRAM cell. Methods/Analysis: The proposed cell has the same architecture as that of read decoupled 7T SRAM cell (RD7T) with an exception of TG instead of access NMOS transistors. This cell is operated in super-threshold region at power supply varying from 0.62V to 0.77V. Findings: Various design metrics of the proposed cell are estimated and compared with RD7T. The proposed cell offers robustness against the process induced variations by providing a 1.1 × narrower spread in read time (TRA) distribution at a cost of 1.23 × penalty in TRA. It also provides 2.06 × narrower spread in read current (IREAD) distribution at the price of 1.13 × penalty in IREAD. It offers 1.42 × lower leakage current and also a 1.06 × lower hold power as compared to that of RD7T. Moreover, it also provides 1.13 × narrower spread in hold power with same read static noise margin (185 mV). Novelty /Improvement: The Monte Carlo based comparative analysis proves that the suggested cell is tolerant to the Vt fluctuations to a great extent.

Size-effects in indium gallium arsenide nanowire field-effect transistors

We fabricate and analyze InGaAs nanowire MOSFETs with channel widths down to 18 nm. Low-temperature measurements reveal quantized conductance due to subband splitting, a characteristic of 1D systems. We relate these features to device performance at room-temperature. In particular, the threshold voltage versus nanowire width is explained by direct observation of quantization of the first sub-band, i.e., band gap widening. An analytical effective mass quantum well model is able to describe the observed band structure. The results reveal a compromise between reliability, i.e., VT variability, and on-current, through the mean free path, in the choice of the channel material.

A human [11C]T-773 PET study of PDE10A binding after oral administration of TAK-063, a PDE10A inhibitor

Phosphodiesterase 10A (PDE10A) is selectively expressed in the striatal regions in the brain and may play a role in modulating dopaminergic and glutamatergic second messenger pathways. PDE10A inhibitors are expected to be useful in treating neuropsychiatric disorders such as schizophrenia and Huntington’s disease. In this study, the brain kinetics of [11C]T-773 in the human brain and test-retest reproducibility of the outcome measures were evaluated. Subsequently, the occupancy of a novel PDE10A inhibitor, TAK-063, was measured using [11C]T-773.Dynamic PET measurements were conducted three times for 12 healthy male subjects after intravenous bolus injection of [11C]T-773: two baseline PETs and one postdose PET (3hours) after oral administration of TAK-063 for four subjects, and one baseline PET and two postdose PET (3hours and 23hours) for eight subjects. Kinetic model analysis was performed with arterial input functions. PDE10A occupancy was calculated as the percent change of the binding specific to PDE10A (Vs) total distribution volume (VT), which was calculated as the VT of the putamen minus the VT of the cerebellum.Regional brain uptake was highest in the putamen. Time-activity curves of the brain regions were described with two tissue-compartment (2TC) models. The mean VT was 5.5±0.7 in the putamen and 2.3±0.5 in the cerebellum in the baseline PET. Absolute VT variability between the two baseline scans was less than 7%. Reproducibility of VT was excellent. PDE10A occupancy in the putamen ranged from 2.8% to 72.1% at 3hours after a single administration of 3 to 1000mg of TAK-063, and increased in a dose- and plasma concentration-dependent manner. At 23hours postdose, PDE10A occupancy in the putamen was 0 to 42.8% following administration of 3 to 100mg of TAK-063. In conclusion, [11C]T-773 showed good characteristics as a PET radioligand for PDE10A in the human brain.

Comparison of different degrees of variability in tidal volume to prevent deterioration of respiratory system elastance in experimental acute lung inflammation

BackgroundVariable ventilation improves respiratory function, but it is not known whether the amount of variability in tidal volume (VT) can be reduced in recruited lungs without a deterioration of respiratory system elastance. MethodsAcute lung inflammation was induced by intratracheal instillation of lipopolysaccharide in 35 Wistar rats. Twenty-eight animals were anaesthetized and ventilated in volume-controlled mode. Lungs were recruited by random variation of VT (mean 6 ml kg−1, coefficient of variation 30%, normal distribution) for 30 min. Animals were randomly assigned to different amounts of VT variability (n+7 for 90 min per group): 30, 15, 7.5, or 0%. Lung function, diffuse alveolar damage, and gene expression of biological markers associated with cell mechanical stress, inflammation, and fibrogenesis were assessed. Seven animals were not ventilated and served as controls for post-mortem analyses. ResultsA VT variability of 30%, but not 15, 7.5, or 0%, prevented deterioration of respiratory system elastance [Mean (SD) −7.5 (8.7%), P<0.05; 21.1 (9.6%), P<0.05; 43.3 (25.9), P<0.05; and 41.2 (16.4), P<0.05, respectively]. Diffuse alveolar damage was lower with a VT variability of 30% than with 0% and without ventilation, because of reduced oedema and haemorrhage. A VT variability of 30, 15, or 7.5% reduced the gene expression of amphiregulin, cytokine-induced neutrophil chemoattractant-1, and tumour necrosis factor α compared with a VT variability of 0%. ConclusionsIn this model of acute lung inflammation, a VT variability of 30%, compared with 15 and 7.5%, was necessary to avoid deterioration of respiratory system elastance and was not associated with lung histological damage.

(Invited) Floating Gate Type SOI-FinFET Flash Memories with Different Channel Shapes and Interpoly Dielectric Materials

The floating gate (FG)-type silicon-on-insulator (SOI)-FinFET flash memories with triangular-fin (TF) and rectangular-fin (RF) channels and with different interpoly dielectric (IPD) materials have been successfully fabricated using (100)- and (110)-oriented SOI wafers and orientation dependent wet etching. The electrical characteristics of the fabricated FG-type SOI-FinFET flash memories including threshold voltage (Vt) variability, program/erase (P/E) speed, memory window, endurance, and data retention at room temperature and 85 oC have been comparatively investigated. It was experimentally found that the TF channel flash memory with an Al2O3-nitride-oxide (ANO) IPD layer shows a higher P/E speed, a larger memory window, and a lower-voltage operation as compared to the RF channel flash memories with the same ANO IPD layer. Such a high performance of the TF-ANO flash memory is due to the high-k effect of the Al2O3 layer and the electric field enhancement at the sharp foot edges of the TF.

A Thermal Method to Reduce the Polysilicon Resistance for Deep Submicron Integration Process

In the ultra-large-scale integration (ULSI) technologies, polysilicon resistors are usually employed in the integrated circuits as a precise analog resistor element for a variety of applications, such as DAC (digital resistor give the solution of the linearity and Rs concerns to analog converter) in analogue circuits [1-3]. Conventionally the polysilicon resistance can be adjusted by ion implantation and post annealing process [4]. For the self-aligned implantation process, the dosage changes which are always utilized to adjust the resistance are feasible to induce the MOS characteristics changes, especially in the submicron process whose short-channel effects (SCE) are much more sensitive to the dosages [5]. In this work, we propose a new inner anneal process in N2ambient after polysilicon re-oxidation to reduce the polysilicon resistance by changing the polysilicon grain size. The test patterns are manufactured on 300mm-diameter wafer by 65-nm 1-poly 7-metal standard CMOS technology. After polysilicon re-oxidation to form oxide film on polysilicon surface, the wafers are annealed at 800oC, 900oC, 950oC and 1000oC in N2ambient, respectively. Fig. 1 shows the process flow and annealing process steps in the flow. After anneal, the polysilicon grain size is measured by X-ray powder diffraction (XRD). And the electric characteristics for NMOS, PMOS and polysilicon resistance are tested. Fig. 2 shows the poly resistance reduction proportion and poly grain size after anneal at 800oC, 900oC, and 1000oC for 5min, and 950oC for 20min in N2 ambient, respectively. Only after annealing at 950oC or above for 5min, the resistance can be obviously reduced, due to the poly grain size increasing. Fig. 3 shows threshold voltages (Vt) variation proportions of NMOS and PMOS owning gate length of 65nm and width 0.12µm after utilizing annealing process at different temperatures. PMOS is more sensitive to the anneal process than NMOS. But after anneal at 950oC or below, the threshold variation for both NMOS and PMOS is less than 5%, which is acceptable for the integration process manufacturing. A new anneal process at N2 ambient to adjust the polysilicon resistance has been proposed. It has been verified that utilizing anneal process at 950oC or below, the 65nm MOS performances can be maintained almost same as before. Consequently, it is considered that the anneal method can be to be applied to the deep submicron integration process.

Estimating energetics in cetaceans from respiratory frequency: why we need to understand physiology.

ABSTRACTThe accurate estimation of field metabolic rates (FMR) in wild animals is a key component of bioenergetic models, and is important for understanding the routine limitations for survival as well as individual responses to disturbances or environmental changes. Several methods have been used to estimate FMR, including accelerometer-derived activity budgets, isotope dilution techniques, and proxies from heart rate. Counting the number of breaths is another method used to assess FMR in cetaceans, which is attractive in its simplicity and the ability to measure respiration frequency from visual cues or data loggers. This method hinges on the assumption that over time a constant tidal volume (VT) and O2 exchange fraction (ΔO2) can be used to predict FMR. To test whether this method of estimating FMR is valid, we measured breath-by-breath tidal volumes and expired O2 levels of bottlenose dolphins, and computed the O2 consumption rate (V̇O2) before and after a pre-determined duration of exercise. The measured V̇O2 was compared with three methods to estimate FMR. Each method to estimate V̇O2 included variable VT and/or ΔO2. Two assumption-based methods overestimated V̇O2 by 216-501%. Once the temporal changes in cardio-respiratory physiology, such as variation in VT and ΔO2, were taken into account, pre-exercise resting V̇O2 was predicted to within 2%, and post-exercise V̇O2 was overestimated by 12%. Our data show that a better understanding of cardiorespiratory physiology significantly improves the ability to estimate metabolic rate from respiratory frequency, and further emphasizes the importance of eco-physiology for conservation management efforts.

Changes in breathing pattern upon 100% oxygen in children at early school age

Nitrogen multiple-breath washout (N2MBW) is an increasingly used tidal breathing test in young children to assess ventilation inhomogeneity. However, the test requires 100% oxygen to perform. We aimed to examine the potential influence of pure oxygen on breathing pattern in school-aged children.We performed tidal breathing measurements under room air followed by N2MBW in 16 former preterm children and 24 healthy controls. We compared tidal volume (VT), coefficient of variation of VT (CVVT), respiratory rate (RR), and minute ventilation (VE) between tidal breathing and N2MBW, and between the start and end of tidal breathing. Mean (range) age was 6.8 (5.9, 9.0) years. VT, RR and VE showed no significant change upon oxygen-exposure, while CVVT significantly decreased by 5% (95% CI: 1.2, 9.0; p=0.012). However CVVT was also the only parameter which significantly decreased during tidal breathing. Overall, pure oxygen has no systematic effect on breathing pattern in young school-aged children. N2MBW can reliably be used as tracer gas in this age group.

Increased ventilatory variability and complexity in patients with hyperventilation disorder.

It has been hypothesized that hyperventilation disorders could be characterized by an abnormal ventilatory control leading to enhanced variability of resting ventilation. The variability of tidal volume (VT) often depicts a nonnormal distribution that can be described by the negative slope characterizing augmented breaths formed by the relationship between the probability density distribution of VT and VT on a log-log scale. The objectives of this study were to describe the variability of resting ventilation [coefficient of variation (CV) of VT and slope], the stability in respiratory control (loop, controller and plant gains characterizing ventilatory-chemoresponsiveness interactions) and the chaotic-like dynamics (embedding dimension, Kappa values characterizing complexity) of resting ventilation in patients with a well-defined dysfunctional breathing pattern characterized by air hunger and constantly decreased PaCO2 during a cardiopulmonary exercise test. Compared with 14 healthy subjects with similar anthropometrics, 23 patients with hyperventilation were characterized by increased variability of resting tidal ventilation (CV of VT median [interquartile]: 26% [19-35] vs. 36% [28-48], P = 0.020; slope: -6.63 [-7.65; -5.36] vs. -3.88 [-5.91; -2.66], P = 0.004) that was not related to increased chemical drive (loop gain: 0.051 [0.039-0.221] vs. 0.044 [0.012-0.087], P = 0.149) but that was related to an increased ventilatory complexity (Kappa values, P < 0.05). Plant gain was decreased in patients and correlated with complexity (with Kappa 5 - degree 5: Rho = -0.48, P = 0.006). In conclusion, well-defined patients suffering from hyperventilation disorder are characterized by increased variability of their resting ventilation due to increased ventilatory complexity with stable ventilatory-chemoresponsiveness interactions.

Sigh-induced changes of breathing pattern in preterm infants.

Sighs are thought to play an important role in control of breathing. It is unclear how sighs are triggered, and whether preterm birth and lung disease influence breathing pattern prior to and after a sigh in infants. To assess whether frequency, morphology, size, and short-term variability in tidal volume (VT) before, during, and after a sigh are influenced by gestational age at birth and lung disease (bronchopulmonary dysplasia, BPD) in former preterm infants and healthy term controls measured at equivalent postconceptional age (PCA). We performed tidal breathing measurements in 143 infants during quiet natural sleep at a mean (SD) PCA of 44.8 (1.3) weeks. A total of 233 sighs were analyzed using multilevel, multivariable regression. Sigh frequency in preterm infants increased with the degree of prematurity and severity of BPD, but was not different from that of term controls when normalized to respiratory rate. After a sigh, VT decreased remarkably in all infants (paired t-test: P < 0.001). There was no major effect of prematurity or BPD on various indices of sigh morphology and changes in VT prior to or after a sigh. Short-term variability in VT modestly increased with maturity at birth and infants with BPD showed an earlier return to baseline variability in VT following a sigh. In early infancy, sigh-induced changes in breathing pattern are moderately influenced by prematurity and BPD in preterm infants. The major determinants of sigh-related breathing pattern in these infants remain to be investigated, ideally using a longitudinal study design.

(Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI)

After decades of research, high-k metal gate has been successfully integrated into CMOS starting with 45nm node. High-k can be integrated using gate first or gate last integration. To continue scaling, the industry has chosen two integration approaches: FINFET with gate last and FDSOI with gate first. FINFET with gate last integration was introduced into production at 22nm node by Intel [1]. FDSOI with gate first integration was introduced into production at 28nm node by ST Microelectronics[2]. There are some common factors impacting threshold voltage (Vt) on both of these integrations such as high-k /metal gate film thickness and composition as well as doping concentration. Beyond that, each integration approach has its own unique challenges that must be overcome to achieve targeted Vt and maintain Vt control. In this work we will highlight those unique challenges and discuss what knobs can be used to achieve targeted Vts and maintain Vt control. In FINFET gate last integration, dummy poly gate was formed first, and then high-k/metal gate stack is deposited after complete removal of the dummy gates. In this integration, gate-fill and gate height are critical for Vt targeting and Vt control. As gate CD become smaller, having void-free gate fill is a challenge. A conventional CVD W-fill is shown to result in voids formation. An alternative approach of W deposition is shown to improve fill and can also be used to modulate Vt. In addition, gate height for FINFET gate last integration is defined by many processing steps. Variation in any of the processing steps could translate into Vt variation. Gate height variation reduction at key contributing steps is important to control the final gate height and ultimately, Vt variation. In gate first integration, it is widely known that oxygen ingress prevention and gate encapsulation are critical for Vt control. It has been reported that undesirable lateral oxygen diffusion is responsible for Vt instability [3]. A conformal, low temperature encapsulation is important to avoid oxygen ingress into the gatestack. As transistor designs increase in complexity, this encapsulation layer must be conformal and not sensitive to wafer loading conditions. Low temperature PEALD SiN gate encapsulation has been developed and shown to be superior to conventional CVD SiN[4]. In addition to these challenges, when integrating high-k gate first in FDSOI and as the SOI layer is thinned down to <15nm, special care must be taken to prevent the erosion of this thin channel. Cleaning steps, oxide growth steps as well as annealing steps may consume or oxidize the already thin channel and need to be tailored to minimize further channel thinning. Furthermore, an additional way to control Vt that is unique to FDSOI integration, namely the concept of back-biasing, will be discussed.

(Plenary) Physical Insights on the Design of UTB Devices, Including FinFETs

A revolution in device design for nanoscale CMOS is now occurring because the conventional bulk-Si MOSFET can no longer be scaled due to channel-doping limitations. Two novel devices with undoped ultra-thin bodies (UTBs), the quasi-planar FinFET, on bulk Si or SOI, and the planar fully depleted (FD) SOI MOSFET, are now the prime candidates for nanoscale CMOS. This paper, based on our recently published textbook on UTB devices [1], overviews the unique physics of these new CMOS devices, and offers insights on their designs, scalabilities, and performance potentials. The characterization of the threshold voltage of the FinFET and the FD-SOI MOSFET is unique and generally complex, but generic, following from the application of Poisson's Equation and Gauss's Law in the undoped UTB. It simplifies for the long symmetrical double-gate (DG) FinFET (Vt ≈ ΦMSf + φc where φc ≈ 0.4V is the surface potential at the threshold condition), and, for the FD-SOI MOSFET, yields Vt(VGbS, ΦMSb) which shows how Vt can be varied via substrate bias and/or doping. Also, Vt is increased by energy quantization, dependent on UTB thickness (tSi, with tSi < 4nm being prohibitive) and transverse electric field, and it is decreased by short-channel effects (SCEs), dependent strongly on tSi. Regarding SCE control, the DG FinFET is superior to the FD-SOI MOSFET which requires substantially thinner tSi. The triple-gate (TG, with a fin-top gate) device is not much better than the DG device in this regard, nor does it offer much Ion improvement due to the prevalent bulk inversion in the undoped UTB. The SCE control is dramatically improved by a gate-source/drain underlap, defined by the source/drain lateral doping profile, that implies an effective channel length (Leff) longer than the gate length (Lg) for weak inversion, but Leff ≈ Lgfor strong inversion. Such optimal design is peculiar to undoped channels. The superior SCE control with FinFETs implies better scalability, and Intel Corp. has chosen [2] this device for its nanoscale CMOS. For vague reasons, it chose bulk Si for the substrate as opposed to SOI. Nonetheless, it appears that SOI will ultimately be needed (for Lg → <10nm), mainly because of unavoidable random variations in the high doping (PTS) density needed at the base of the fin to stop drain-source punch-through leakage. This leakage current is examined, in terms of the PTS doping density (~1018cm-3 is optimal), and variations in Vt and Iondue to the random PTS variations clearly imply problems in nanoscale bulk-Si FinFETs. Further, the PTS variations can undermine the control of the G-S/D underlap. The examination of the bulk-Si vs. SOI FinFET issue is concluded by noting a processing issue for FinFETs on SOI wafers, and suggesting that a local-SOI structure in bulk Si could be the ultimate solution. The physical insights overviewed herein imply a set of pragmatic FinFET design criteria that, we believe, can simplify the technology without undermining the CMOS performance much. They include the following: use an SOI structure (e.g., local in bulk Si); use an undoped UTB/channel with tSi > 4nm; use DG as opposed to TG; use no high-k dielectric (as implied by effects of strong bulk inversion); use one ~midgap metal gate for LP, and perhaps dual gates for HP; use optimal G-S/D underlap; use no channel strain (carrier mobilities can be high without it); and possibly use optimal S/D processing for Vtcontrol (and underlap). SRAM simulations demonstrate the viability of such pragmatic FinFET design.

Highly Vt tunable and low variability triangular fin-channel MOSFETs on SOTB

Triangular fin (Tri-Fin) channel double-gate (DG) MOSFETs were successfully fabricated on (100) SOTB wafers using orientation dependent wet etching, and their electrical characteristics were systematically compared to the rectangular fin (Rec-Fin) ones by RIE. Thanks to the wide bottom area and the suppressed line edge roughness of Tri-Fins by the wet process, a higher threshold voltage (Vt) tunability and a smaller Vt variation were obtained as compared to the Rec-Fin ones. Moreover, the wet processed Tri-Fin devices provide a damage-free BOX layer, which is useful for the fabrication of multiple Vt devices with an ultrathin BOX layer.

Quantitative amyloid imaging using image-derived arterial input function.

Amyloid PET imaging is an indispensable tool widely used in the investigation, diagnosis and monitoring of Alzheimer’s disease (AD). Currently, a reference region based approach is used as the mainstream quantification technique for amyloid imaging. This approach assumes the reference region is amyloid free and has the same tracer influx and washout kinetics as the regions of interest. However, this assumption may not always be valid. The goal of this work is to evaluate an amyloid imaging quantification technique that uses arterial region of interest as the reference to avoid potential bias caused by specific binding in the reference region. 21 participants, age 58 and up, underwent Pittsburgh compound B (PiB) PET imaging and MR imaging including a time-of-flight (TOF) MR angiography (MRA) scan and a structural scan. FreeSurfer based regional analysis was performed to quantify PiB PET data. Arterial input function was estimated based on coregistered TOF MRA using a modeling based technique. Regional distribution volume (VT) was calculated using Logan graphical analysis with estimated arterial input function. Kinetic modeling was also performed using the estimated arterial input function as a way to evaluate PiB binding (DVRkinetic) without a reference region. As a comparison, Logan graphical analysis was also performed with cerebellar cortex as reference to obtain DVRREF. Excellent agreement was observed between the two distribution volume ratio measurements (r>0.89, ICC>0.80). The estimated cerebellum VT was in line with literature reported values and the variability of cerebellum VT in the control group was comparable to reported variability using arterial sampling data. This study suggests that image-based arterial input function is a viable approach to quantify amyloid imaging data, without the need of arterial sampling or a reference region. This technique can be a valuable tool for amyloid imaging, particularly in population where reference normalization may not be accurate.

SiGe channel deposition by batch epitaxy

Batch epitaxy has been introduced for high volume manufacturing of SiGe channels in order to reduce the cost for this epitaxial process by a factor of 3. Beside cost, SiGe channel deposition by batch epitaxy offers many benefits for manufacturing. The stability of the process and the reduced variability of the SiGe thickness greatly improve the variation of VT. The batch epitaxy process does not show a pattern loading effect for SiGe thickness reducing the complexity for manufacturing significantly. However, since the tool concept is very different to that of the widely used single wafer tools, there are some tool specific issues that need to be managed. The wafer backside is critical for batch epitaxy. A nitride backside facing the front side of the wafer results in a clear degradation of the uniformity and a change of the morphology of the SiGe channel compared to that facing a Si backside. The thermal rounding is more pronounced for the channels deposited in a batch tool for both large and narrow width devices. The device parameters of the large width device are not affected by thermal rounding but the performance of the narrow width device is clearly degraded. The thin SiGe layer at the edge of the channel driven by thermal rounding affects the VT and thus the effective device width. An in-situ etching before SiGe deposition to avoid thermal rounding was not feasible due to defects issues which were induced by the wafer backside. Finally a thermal rounding of the Si by an aggressive H2 bake before SiGe deposition improves the SiGe channel uniformity and recovers the performance degradation of the narrow width device partly.

Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories

Floating-gate (FG)-type three-dimensional (3D) fin channel flash memories with triangular fin (TF) and rectangular fin (RF) channels and different interpoly dielectric (IPD) materials have been successfully fabricated using (100)- and (110)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. The electrical characteristics of the fabricated FG-type 3D fin channel flash memories including threshold voltage (Vt) variability, program/erase (P/E) speed, memory window, endurance, and data retention at room temperature and 85 °C have been comparatively investigated. A higher P/E speed, a larger memory window, and a lower-voltage operation are experimentally obtained in the TF channel flash memories with an Al2O3–nitride–oxide (ANO) IPD layer (TF-ANO) than in the RF channel ones with the same ANO IPD layer (RF-ANO) and the TF channel ones with an oxide–nitride–oxide (ONO) IPD layer (TF-ONO). The larger memory window and lower-voltage operation of TF-ANO flash memories are due to the high-k effect of the Al2O3 layer and the electric field enhancement at the sharp foot edges of the TF channels. It was also found that data retention for all fabricated FG-type 3D fin channel flash memories shows a weak dependence on temperature.

A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the VT variation among cells and reduce the total programming time.

Effects of different levels of pressure support on intra-individual breath-to-breath variability.

Evidence exists that during pressure support ventilation (PSV), the addition of an extrinsic (ie, ventilator-generated) breath-to-breath variability (BBV) of breathing pattern improves respiratory function. If BBV is beneficial per se, choosing the PS level that maximizes it could be considered a valid strategy for conventional PSV. In this study, we evaluated the effect of different PS levels on intrinsic BBV in acutely ill, mechanically ventilated subjects to determine whether a significant relationship exists between PS level and BBV magnitude. Fourteen invasively mechanically ventilated subjects were prospectively studied. PS was adjusted at 20 cm H2O and sequentially reduced to 15, 10, and 5 cm H2O. Arterial blood gas analysis and pressure at 0.1 s after the onset of inspiration (P0.1) were measured at each PS level. Airway and esophageal pressure and air flow were continuously recorded. Peak inspiratory flow, tidal volume (VT), breathing frequency, and pressure-time product (PTP) were calculated on a breath-by-breath basis. The breathing pattern variability was assessed by the coefficient of variation of the time series of VT, peak inspiratory flow, and breathing frequency from ∼ 60 consecutive breath cycles at each PS level. A general linear model for repeated measures was applied, with PS as an independent factor. A significance level of .05 was considered. Despite a large inter-individual difference in all measured variables (P < .001), the coefficient of variation was as low as 30%, and no significant differences in the coefficient of variation of peak inspiratory flow, breathing frequency, and VT between PS levels were observed (P > .15). Additionally, a significant increase in P0.1, PTP, and breathing frequency (P < .01) and a reduction in VT (P < .001) were observed with PS reduction. Despite a significant increase in spontaneous activity with PS reduction, BBV was not influenced by the PS level and was as low as 30% for all evaluated parameters.

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB (silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al2O3 blocking layer instead of a SiO2 blocking layer. It was also confirmed that the variability of Vt before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials.