Voltage SRAM Research Articles

Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node

Binary Neural Networks (BNNs) have been shown to be robust to random bit-level noise, making aggressive voltage scaling attractive as a power-saving technique for both logic and SRAMs. In this work, we introduce the first fully programmable IoT end-node system-on-chip (SoC) capable of executing software-defined, hardware-accelerated BNNs at ultra-low voltage. Our SoC exploits a hybrid memory scheme where error-vulnerable SRAMs are complemented by reliable standard-cell memories to safely store critical data under aggressive voltage scaling. On a prototype in 22nm FDX technology, we demonstrate that both the logic and SRAM voltage can be dropped to 0.5V without any accuracy penalty on a BNN trained for the CIFAR-10 dataset, improving energy efficiency by 2.2X w.r.t. nominal conditions. Furthermore, we show that the supply voltage can be dropped to 0.42V (50% of nominal) while keeping more than 99% of the nominal accuracy (with a bit error rate ~1/1000). In this operating point, our prototype performs 4Gop/s (15.4 Inference/s on the CIFAR-10 dataset) by computing up to 13 binary ops per pJ, achieving 22.8 Inference/s/mW while keeping within a peak power envelope of 674uW - low enough to enable always-on operation in ultra-low power smart cameras, long-lifetime environmental sensors, and insect-sized pico-drones.

A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications

Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.

Simulation-Based Study of High-Density SRAM Voltage Scaling Enabled by Inserted-Oxide FinFET Technology

A scheme for precisely adjusting the drive strength of an inserted-oxide FinFET (iFinFET) comprising two nanowire (NW) channel regions that are separated by a thin oxide layer, to enhance the manufacturing yield of a minimally sized six-transistor static random access memory (6T-SRAM) cell, is investigated in this paper. The 3-D process simulations show that the upper NW channel region can be selectively rendered nonconducting by dopant ion implantation followed by thermal annealing so that its threshold voltage is greater than the supply voltage ( ${V}_{\text {DD}}$ ). Furthermore, the position of the inserted-oxide layer can be adjusted to balance the tradeoff between the read stability and write-ability to achieve the lowest minimum cell operating voltage ( ${V}_{\text {min}}$ ). Using a compact transistor model calibrated to 3-D device simulations, doped iFinFET technology is projected to enable ${V}_{\text {min}}$ of a minimally sized 6T-SRAM cell to be substantially lower than ${V}_{\text {DD}}$ , eliminating the need for write-assist circuitry and lowering power consumption.

A novel 8T SRAM with improved cell density

Low voltage and high-density SRAM memory creates new challenges such as stability and sense margin. Conventional decoupled 8T SRAM cell has improved read stability but small sense margin and high leakage power which makes it unsuitable for small supply and high density memories. Proposed decoupled 8T SRAM cell improves sense margin during reading by reducing data leakage current of neighboring SRAM cells which are OFF and write stability by using negative bit line scheme. It is evident from the simulation results that proposed 8T SRAM minimizes leakage current by 49.2% when compared to conventional 8T SRAM cell. It gives stable read for 20.2 K cells per bitline at 0.8 V at room temperature but conventional 8T SRAM can give successful read for 5.83 K cells.

Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors

Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM and discover the variance among different sizing configuration and asymmetric minimum voltage requirements between read and write operations. We leverage this asymmetric property i n near-threshold processors equipped with voltage boosting capability by proposing an opportunistic dual-supply switching scheme with a write aggregation buffer. Our results show that proposed technique improves energy efficiency by more than 21.45% with approximate 10.19% performance speed-up.

A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD–SOI

A 128-kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in 28-nm FD-SOI technology is presented. An ideal power management scenario in a single supply system is achieved by permanently keeping the storage elements in the vicinity of the retention voltage. Performance and reliability is regained by boosting the voltage on critical nodes. The cost of voltage boost generation unit is minimized by 66 low-power and area efficient ON-chip charge pumps, i.e., 64 for boosting the voltages on write-bitlines and two for the wordlines. The charge pump energy overhead is reduced by introducing a new boost paradigm with an on-demand activation mechanism that generates the required boost level in a single clock cycle. A sense amplifier-less read architecture enables a reliable and high performance read operation. Measurements identify several meritorious metrics. The minimum read energy is identified as 8.4fJ/bit-access, achieved for 90-MHz operation at 0.3V. Furthermore, the minimum operating voltage is measured as 240mV, and data is retained in ultra-low voltage regime, ranging down to 0.2V. The bitcell area, implemented using standard design rules, is 0.261 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The entire memory, including the digital test circuitry, occupies 0.161 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of chip area.

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

Ultra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boosting technique for enhancing the sensing margin. The proposed technique automatically tracks process, temperature and voltage (PVT) variations for robust sensing margin enhancement. A test chip fabricated in 65 nm CMOS technology shows that the proposed scheme significantly enlarges the sensing margin compared to the conventional bitline sensing scheme. It also achieves the minimum operating voltage of 0.18 V and the minimum energy consumption of 0.92 J/access at 0.4 V.

Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing

This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional on-chip SRAM for near-threshold voltage computing. It focuses on area- and energy-efficiency using minimum height standard-cells. Unlike conventional SCMs, the proposed SCM has standard-cells with a minimum possible cell height allowed by the logic design rule of the target technology. This paper also presents energy efficient readout and write schemes for reducing dynamic energy consumption. Post layout simulation using a 65-nm FD-SOI technology shows that the proposed SCM achieves area efficiency of 6.82μm2 per bit (682F2 per bit), which is 20% less than that of the state of the art SCMs. The results also show that the energy consumption of the proposed SCM is 31% less than that of the state of the art low voltage SRAMs.

Novel tri-independent-gate FinFET for multi-current modes control

In this paper, a novel tri-independent-gate (TIG) FinFET is presented for multi-current modes control for the first time. The entire integration flow of proposed TIG FinFET is fully compatible with the mainstream gate-first HKMG FinFET process. Five kinds of ON state modes and threshold voltages can be offered by TIG FinFET without additional voltage sources, and it is demonstrated to have a great potential in dynamic voltage SRAM design. The critical electrical parameters of TIG FinFET in different modes are fully investigated with TCAD simulation and compared to the traditional FinFET. TIG FinFET with double fins is found to possess a distinct different output and capacitance characteristics with single fin FinFET. The underlying physical mechanisms are analyzed and investigated in detail.

A Leakage Compensation Design for Low Supply Voltage SRAM

A leakage current compensation design for nanoscale SRAMs is proposed in this paper. The proposed compensation design is composed of a leakage current sensor, which generates a warning signal if the leakage is over a predefined threshold, and a compensation circuit following the sensor, which will be activated to speed up the read operation. At 0.6 V system voltage, the proposed compensation design reduces 27.86% of the average power dissipation, and 54.88% of the read delay at the expense of 3.64% area overhead. The proposed Static Random-Access Memory is implemented using the TSMC 40-nm CMOS logic technology. The energy per access is measured to be 0.9411 pJ given a 600-mV power supply and a 54-MHz system clock rate.

Additive-calibration scheme for leakage compensation of low voltage SRAM

Additive-calibration scheme for leakage compensation of low voltage SRAM

Analysis of static noise margin improvement for low voltage SRAM composed of nano-scale MOSFETs with ideal subthreshold factor and small variability

An ultra-low voltage performance of nanowire-transistors-based SRAM cell is investigated using the SPICE model parameters extracted from measurement data. The impact of S-factor and threshold voltage variations on the static noise margin and the minimum operating voltage is evaluated in nanowire transistor as well as in planar bulk transistor and quasi-planar bulk transistor. The performance benefits of undoped nanowire-transistor-based SRAM are measured in terms of the read stability for low voltage and low off leakage current operation.

New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET

New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET

Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation

This paper analyzes and compares the stability, margin, performance, and variability of ultrathin-body (UTB) SOI 6T SRAM cells operating near the subthreshold region with different threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) design. Our results indicate that UTB SOI 6T SRAM cell using low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> devices (|V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> | = 0.19 V) shows a comparable read static noise margin (RSNM), 41% improvement in σRSNM, 84% improvement in write static noise margin (WSNM), and 67% improvement in σWSNM as compared with the case using higher V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> devices (|V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> | = 0.49 V). As V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> decreases (work function moves to the band edge), the “cell” access time improves significantly with correspondingly higher standby leakage. For low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> devices (|V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> | = 0.19 V), it is shown that lowering bit-line precharge voltage by 50 mV reduces the standby leakage by 20%. Our study suggests that the lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> devices operating slightly into super-threshold region improve the stability/variability significantly and offer higher performance for ultralow voltage SRAM applications.

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the highest energy-efficient operation of low voltage SRAM, the new CSHBL technique and CCC techniques, which is the improved version of the CSHBL, have been proposed. An SRAM fabricated using 65 nm technology adopting the CSHBL achieved an energy consumption of 26.4 pJ/Access/Mbit, and that of 13.8 pJ/Acess/Mbit is achieved by the SRAM macro that adopted CCC with 40 nm technology. This energy consumption is lower than values in previous works.

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control

An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

A Comparative Study of Single- and Dual-Threshold Voltage SRAM Cells

In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high- Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively.

A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform

The advanced-DFM RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability(@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 cell/bit with the complementary dynamic memory operation and has the 1 cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (sense synchronized write) peripheral circuit technologies are also adopted for the low voltage and FV controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.

Trends in low-power RAM circuit technologies

Trends in low-power circuit technologies of CMOS RAM chips are reviewed in terms of three key issues: charging capacitance, operating voltage, and dc current. The discussion includes a general description of power sources in a RAM chip, and covers both DRAMs and SRAMs. In DRAMs, successive circuit advancements have produced a power reduction equivalent to two to three orders of magnitude over the last decade for a fixed memory capacity chip. Coupled with the low-power advantage of CMOS circuits, two technologies have been the major contributors to power reduction: lower charging capacitance due to partial activation of multi-divided arrays that use multi-divisions of data and word lines; and lower operating voltage resulting from external power supply reduction, half-V/sub DD/ precharging and on-chip voltage down converting scheme. In SRAMs, partial activation of a multi-divided word line drastically reduces the dc current from the data-line load to the selected cell. In addition to advances in the sense amplifier circuit, an auto power down scheme that uses address transition detection for word driver and column circuitry further reduces the dc current. It is also shown that to design ultralow voltage DRAMs and SRAMs, the application of subthreshold current reduction circuits (such as source-gate back biasing) to cell and iterative circuit blocks will be indispensable in the future.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>